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pd6710/?22 isa-to-pc-card (pcmcia) controllers datasheet the pd6710 and pd6722 are single-chip pc card (pcmcia) controller solutions capable of controlling one (pd6710) or two (pd6722) pc card sockets. the chips are compliant with pc card standard, pcmcia 2.1, and jeida 4.1 and are optimized for use in embedded applications and notebook/handheld/mobile computer systems where reduced form factor and low power consumption are critical design objectives. with the pd6710, a complete pc card solution with power-control logic can occupy less than 1.5 square inches (excluding the socket connector). with the pd6722, a complete dual-socket pc card solution with power-control logic can occupy less than 2 square inches (excluding socket connectors). the chips employ energy-efficient mixed-voltage technology that can reduce system power consumption by over 50 percent. the chips also provide: a low-power dynamic mode, which automatically stops the internal clock during periods of card inactivity; a software-controlled suspend mode, which dramatically reduces power by disabling most of the internal circuitry and stopping data transactions to the pc cards; and a hardware-controlled super suspend mode, which reduces current to the a range. personal computer applications typically access pc cards through a third-party socket/card- services software interface. to assure full compatibility with industry-standard socket/card- services software and pc card applications, the register set in the pd6710 and pd6722 is a superset of the intel ? 82365sl register set. the chips provide fully buffered pc card interfaces, meaning that no external logic is required for buffering signals to/from the interface, and power consumption can be controlled by limiting signal transitions on the pc card bus. as of may 2001, this document replaces the basis communications corp. document cl-pd6710/?22 ? isa-to-pc-card host adapters . may 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pd6710 or pd6722 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, may 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 isa-to-pc-card (pcmcia) controllers ? pd6710/?22 contents 1.0 product features ........................................................................................................9 2.0 general conventions ..............................................................................................11 2.1 numbers and units..............................................................................................11 3.0 pin information ..........................................................................................................12 3.1 pin diagrams.......................................................................................................13 3.2 pin description conventions ...............................................................................14 3.3 pin descriptions ..................................................................................................16 3.4 power-on configuration summary .....................................................................25 4.0 introduction ................................................................................................................27 4.1 system architecture ............................................................................................27 4.1.1 pc card basics ......................................................................................27 4.1.2 pd67xx windowing capabilities ...........................................................27 4.1.3 pd67xx functional blocks ....................................................................30 4.1.4 interrupts ................................................................................................30 4.1.5 alternate functions of interrupt pins ......................................................31 4.1.6 general-purpose strobe feature ...........................................................32 4.1.7 voltage sense pins ................................................................................32 4.1.8 pd67xx power management ................................................................32 4.1.9 socket power management features ....................................................34 4.1.10 write fifo..............................................................................................35 4.1.11 bus sizing ..............................................................................................35 4.1.12 programmable pc card timing .............................................................36 4.1.13 dma mode operation for the pd6722 ...................................................36 4.1.14 selective data drive for i/o windows ....................................................36 4.2 host access to registers ....................................................................................36 4.3 power-on setup..................................................................................................38 5.0 register description conventions ....................................................................39 6.0 operation registers ................................................................................................41 6.1 index....................................................................................................................41 6.2 data.....................................................................................................................44 7.0 chip control registers ..........................................................................................46 7.1 chip revision ......................................................................................................46 7.2 interface status ...................................................................................................47 7.3 power control......................................................................................................48 7.4 interrupt and general control..............................................................................51 7.5 card status change............................................................................................52 7.6 management interrupt configuration...................................................................54 7.7 mapping enable ..................................................................................................55 8.0 i/o window mapping registers ..........................................................................58 8.1 i/o window control .............................................................................................58 8.2 system i/o map 0 ? 1 start address low .............................................................59
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 4 datasheet 8.3 system i/o map 0 ? 1 start address high ............................................................ 60 8.4 system i/o map 0 ? 1 end address low .............................................................. 60 8.5 system i/o map 0 ? 1 end address high ............................................................. 61 8.6 card i/o map 0 ? 1 offset address low ............................................................... 62 8.7 card i/o map 0 ? 1 offset address high .............................................................. 62 9.0 memory window mapping registers ............................................................... 64 9.1 system memory map 0 ? 4 start address low..................................................... 64 9.2 system memory map 0 ? 4 start address high .................................................... 65 9.3 system memory map 0 ? 4 end address low ...................................................... 66 9.4 system memory map 0 ? 4 end address high ..................................................... 66 9.5 card memory map 0 ? 4 offset address low ....................................................... 67 9.6 card memory map 0 ? 4 offset address high ...................................................... 68 10.0 extension registers ................................................................................................ 70 10.1 misc control 1 ..................................................................................................... 70 10.2 fifo control ....................................................................................................... 72 10.3 misc control 2 ..................................................................................................... 72 10.4 chip information.................................................................................................. 74 10.5 ata control......................................................................................................... 75 10.6 extended index ................................................................................................... 77 10.7 extended data .................................................................................................... 77 10.7.1 data mask 0 ? 1 ....................................................................................... 78 10.7.2 extension control 1 (pd6722 only, formerly dma control) ................... 78 10.7.3 maximum dma acknowledge delay (pd6722 only) .............................. 79 10.7.4 external data (pd6722 only, socket a, index 2fh) ............................... 81 10.7.5 external data (pd6722 only, socket a, index 6fh) ............................... 82 10.7.6 extension control 2 (pd6722 only) ........................................................ 83 11.0 timing registers ...................................................................................................... 84 11.1 setup timing 0 ? 1 ............................................................................................... 84 11.2 command timing 0 ? 1......................................................................................... 85 11.3 recovery timing 0 ? 1 .......................................................................................... 86 12.0 ata mode operation .............................................................................................. 88 13.0 using gpstb pins for external port control (pd6722 only) 91 13.1 control of gpstb pins ....................................................................................... 91 13.2 example implementations of gpstb-controlled read and write ports............. 93 13.3 gpstb in suspend mode ................................................................................... 94 14.0 vs1# and vs2# voltage detection .................................................................... 95 15.0 dma operation (pd6722 only) ............................................................................ 97 15.1 dma capabilities of the pd6722......................................................................... 97 15.2 dma-type pc card cycles ................................................................................ 97 15.3 isa bus dma handshake signal ........................................................................ 98 15.4 configuring the pd6722 registers for a dma transfer ...................................... 98 15.4.1 programming the dma request pin from the card ............................... 98 15.4.2 configuring the socket interface for i/o ................................................. 99
datasheet 5 isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 15.4.3 preventing dual interpretation of dma handshake signals...................99 15.4.4 turning on dma system .....................................................................100 15.4.5 the dma transfer process ..................................................................100 15.4.6 terminal count to card at conclusion of transfer ..............................100 16.0 electrical specifications ......................................................................................101 16.1 absolute maximum ratings...............................................................................101 16.2 dc specifications ..............................................................................................101 16.3 ac timing specifications ..................................................................................104 16.4 isa bus timing..................................................................................................104 16.4.1 reset timing ........................................................................................107 16.4.2 system interrupt timing .......................................................................107 16.4.3 general-purpose strobe timing (pd6722 only)...................................108 16.4.4 input clock specification ......................................................................108 16.4.5 pc card bus timing calculations ........................................................109 17.0 package specifications .......................................................................................121 17.1 144-pin lqfp package.....................................................................................121 17.2 208-pin mqfp package....................................................................................122 17.3 208-pin lqfp package.....................................................................................123 18.0 order numbers example .....................................................................................124 19.0 appendix a ...............................................................................................................125 19.1 register summary tables.................................................................................125 19.1.1 operation registers .............................................................................125 19.2 chip control registers ......................................................................................125 19.3 i/o window mapping registers.........................................................................127 19.4 memory window mapping registers.................................................................129 19.5 extension registers ..........................................................................................130 19.6 timing registers ..............................................................................................133 index ............................................................................................................................... ........135
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 6 datasheet figures 1 system block diagram........................................................................................ 10 2 pc card controller form factor ......................................................................... 10 3 pd6710 pin diagram ......................................................................................... 13 4 pd6722 pin diagram .......................................................................................... 14 5 memory window organization ............................................................................ 29 6 i/o window organization .................................................................................... 29 7 functional block diagram ................................................................................... 30 8 indexed 8-bit register structure ......................................................................... 37 9 indexed 8-bit register example.......................................................................... 37 10 device/socket/register index space.................................................................. 42 11 pulse mode interrupts ......................................................................................... 71 12 selection of acknowledge time-out interval ....................................................... 80 13 example gpstb write port (extension control 2 bits 4:3 are ? 10 ? ) .................... 93 14 example gpstb read port (extension control 2 bits 4:3 are ? 01 ? ).................... 93 15 vs1# and vs2# sensing on a pd6722 (socket b extension control 2 bit 3 is ? 1 ? ) ........................................................... 96 16 dma handshake connections to the isa bus to make the pd6722 dma-capable.................................................................... 98 17 card dma request and acknowledge handshake with terminal count ........... 99 18 bus timing ? isa bus...................................................................................... 106 19 reset timing ..................................................................................................... 107 20 pulse mode interrupt timing ............................................................................. 108 21 general-purpose strobe timing ....................................................................... 108 22 input clock specification................................................................................... 109 23 memory read/write timing .............................................................................. 111 24 word i/o read/write timing ............................................................................. 113 25 pc card read/write timing when system is 8-bit (sbhe tied high) ............ 114 26 normal byte read/write timing........................................................................ 115 27 16-bit system to 8-bit i/o card: odd byte timing ............................................ 116 28 dma read cycle timing................................................................................... 117 29 dma write cycle timing ................................................................................... 119 30 dma request timing ........................................................................................ 120
datasheet 7 isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 tables 1 isa bus interface pins ........................................................................................16 2 socket interface pins ..........................................................................................20 3 general-purpose strobe / voltage sense pins ...................................................24 4 power control pins..............................................................................................24 5 power and ground pins ......................................................................................25 6 pin usage summary ...........................................................................................25 7 chip configuration at power-up for socket support ...........................................26 8 pd67xx power-management modes .................................................................34 9 16-bit mode operation ........................................................................................35 10 8-bit mode operation ..........................................................................................35 11 index registers ...................................................................................................42 12 enabling of socket power controls.....................................................................49 13 enabling of outputs to card socket ....................................................................49 14 maximum dma acknowledge delay register values.........................................80 15 functions of socket a external data register ....................................................81 16 functions of socket b external data register (pd6722 only) ............................82 17 ata pin cross-reference ...................................................................................88 18 registers for control and data of gpstb pins...................................................91 19 four card cycle types for dma-type pc card interface ..................................97 20 general dc specifications ................................................................................101 21 pc card bus interface dc specifications .........................................................101 22 isa bus interface dc specifications .................................................................102 23 power control interface (+5v powered) dc specifications ..............................103 24 operating current specifications ......................................................................103 25 list of ac timing specifications........................................................................104 26 isa bus timing..................................................................................................104 27 reset timing .....................................................................................................107 28 pulse mode interrupt timing .............................................................................107 29 general-purpose strobe timing........................................................................108 30 input clock specification ...................................................................................108 31 memory read/write timing (word access) .....................................................111 32 word i/o read/write timing ............................................................................112 33 pc card read/write timing when system is 8-bit ..........................................113 34 normal byte read/write timing.......................................................................114 35 16-bit system to 8-bit i/o card: odd byte timing ............................................115 36 dma read cycle timing (pd6722 only) ..........................................................116 37 dma write cycle timing (pd6722 only) ..........................................................118 38 dma request timing (pd6722 only) ...............................................................119
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 8 datasheet revision history revision date description 1.0 may 2001 initial release.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 9 1.0 product features ? single-chip pc card (pcmcia) controllers direct connection to isa (pc at) bus and one or two pc card sockets compliant with pc card standard, pcmcia 2.1, and jeida 4.1 82365sl-compatible register set, exca ? -compatible automatic low-power dynamic mode for lowest active power consumption programmable suspend mode hardware-enabled super suspend mode five programmable memory windows per socket and two programmable i/o windows per socket programmable card access cycle timing 8- or 16-bit system bus interface 8- and 16-bit pc card interface support pcmcia-ata and ture-ide disk interface support dma support (pd6722) card-voltage sense support pc card activity indicator mixed-voltage operation (3.3/5.0 v) single-socket interface: 144-pin lqfp for smallest form factor (pd6710) dual-socket interface: 208-pin mqfp or lqfp (pd6722) embedded and mobile systems design priorities supporting features small form factor single-chip solutions no external buffers for host or socket efficient board layout minimum power consumption automatic low-power dynamic mode hardware- and software-controlled suspend modes mixed-voltage operation high performance write cache programmable timing supports more cards, faster reads and writes automatic bus sizing for 8- or 16-bit dma available with the pd6722 hardware and software compatibility compliant with pc card standard, pcmcia 2.1, and jeida 4.1 82365sl a-step register-compatible, exca ? -compatible
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 10 datasheet figure 1. system block diagram figure 2. pc card controller form factor isa (at) bus pc card socket 1 pc card socket 2 pd6710 144-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p c c a r d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p c c a r d (pd6722) pd6722 208-pin card 1 3/8" pd6710 144-pin lqfp 1" v cc v pp and switch- cir- pd6722 208-pin ing 1 9/16" 1 1/4" cuitry card v cc v pp and switch- cir- ing cuitry mqfp or lqfp
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 11 2.0 general conventions the following general conventions apply to this document. throughout this document, pd67xx means pd6710 and pd6722. bits within words and words within various memory spaces are generally numbered with a 0 (zero) as the least-significant bit or word. for example, the least-significant bit of a byte is bit 0, while the most-significant bit is bit 7. in addition, number ranges for bit fields and words are presented with the most-significant value first. thus, when discussing a bit field within a register, the bit number of the most-significant bit is written first, followed by a colon (:) and then the bit number of the least-significant bit; as in, bits 7:0. in this document, the names of the pd67xx internal registers are boldfaced. for example, chip revision and power control are register names. the names of bit fields are written with initial uppercase letters. for example, card power on and battery voltage detect are bit field names. 2.1 numbers and units the unit kbyte designates 1024 bytes (2 10 ). the unit mbyte designates 1,048,576 bytes (2 20 ). the unit gbyte designates 1,073,741,824 bytes (2 30 ). the unit hz designates hertz. the unit khz designates 1000 hz. the unit mhz designates 1,000,000 hz. the unit ms designates millisecond. the unit s designates microsecond. the unit ns designates nanosecond. the unit ma designates milliampere. the unit v immediately following a number designates volt. hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. for example, 14h and 03cah are hexadecimal numbers. binary numbers are enclosed in single quotation marks when in text. for example, ?11? is a binary number. numbers not appended with an h nor enclosed by single quotation marks are decimal. in addition, a capital letter x is used within numbers to indicate digits ignored by the pd67xx within the current context. for example, ?101xx01? is a binary number with bits 3:2 ignored.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 12 datasheet 3.0 pin information the pd6710 is available in a 144-pin vqfp (very tight-pitch quad flat pack) component package and the pd6722 is available in either a 208-pin pqfp (plastic quad flat pack) component package or a 208-pin vqfp component package. the interface pins can be divided into five groups: isa (or isa-like) bus interface pins pc card socket interface pins (one or two sets) general-purpose strobe / voltage sense pins power control pins power and ground pins refer to figure 3 for the pd6710 and figure 4 for the pd6722 pin diagrams. the pin assignments for the groups of interface pins are shown in table 1 through table 5 .
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 13 3.1 pin diagrams figure 3. pd6710 pin diagram pd6710 144-pin lqfp sd6 isa_vcc pwrgood n/c vpp_vcc -vpp_valid -vcc_3 -vcc_5 socket_vcc -reg d3 -cd1 d4 d11 d5 d12 d6 d13 gnd d7 -iord -ce1 d15 a10 -ce2 -oe a11 a9 a8 a17 a14 a19 -we a20 a22 a15 a16 a12 a24 a7 a25 a6 a5 reset a4 -wait a3 -inpack a1 a2 bvd2/-spkr/-led a0 d0 d8 d1 bvd1/-stschg/-ri d2 d10 sd13 sd14 wp/-iois16 sd12 isa_vcc sd11 sd10 sd9 memw* memr* la17 sd8 la18 irq14 la19 irq15/ri_out* la20 irq12/led_out* la21 irq11 la22 iocs16* memcs16* sa5 sa0 sa1 iow* sa6 irq3 sa7 irq4 irq5 sa9 sa10 irq7 sa11 refresh* sa13 sa14 sa8 sa15 ior* spkr_out*/c_sel la23 irq10 sa16 sd1 -cd2 d9 d14 -iowr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 -intr sd7 irq9 sd5 sd4 sd3 sd2 zws* sd0 gnd iochrdy aen sa12 sa4 ale sa3 sa2 clk sbhe* a23 a21 rdy/-ireq vpp_pgm isa_vcc +5v socket_vcc +5v gnd gnd 5v_det core_vdd sd15 gnd socket_vcc core_vdd a13 a18 gnd
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 14 datasheet 3.2 pin description conventions the following conventions apply to the pin description tables in ? pin descriptions ? on page 16 : a dash (-) at the beginning of a pin name indicates an active-low signal for the pc card bus. figure 4. pd6722 pin diagram 2 3 4 5 6 7 160 159 158 157 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 a_d9 a_d2 a_wp/-iois16 64 65 67 68 69 70 71 72 73 74 75 a_-cd2 b_-reg b_d3 b_-cd1 b_d4 b_d11 b_d5 b_d12 42 43 44 45 46 47 48 49 51 50 52 66 98 99 100 101 102 103 104 122 124 125 126 127 128 129 130 105 131 132 133 134 156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 135 161 162 163 164 165 166 167 168 169 170 171 172 173 174 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 201 202 203 204 205 206 207 208 a_-reg a_-vcc_5 a_-vcc_3 -vpp_valid a_vpp_vcc a_vpp_pgm b_-vcc_5 b_-vcc_3 b_vpp_vcc b_vpp_pgm +5v -intr k r_out*/c_sel isa_vcc sd7 sd6 irq9 sd5 sd3 sd2 zws* sd1 sa5 gnd aen iochrdy iow* ior* sa16 sa15 sa14 refresh* sa6 sa12 sa11 irq7 sa10 sa9 irq5 sa8 irq4 sa7 irq3 sa4 ale sa3 sa2 clk sa1 sa0 sbhe* irq10 la22 irq11 la21 irq15/ri_out* la19 irq14 la18 isa_vcc la17 memr* sd9 gnd sd8 sd10 b_-oe b_a1 b_bvd2/-spkr/-led b_a0 b_bvd1/-stschg/-ri gnd b_d0 b_d8 b_d1 b_d2 b_d10 b_wp/-iois16 core_vdd sd15 sd14 sd13 sd12 b_a2 b_-inpack b_a21 b_reset b_a6 b_a4 b_rdy/-ireq b_-we b_a20 b_a5 b_a16 b_-ce2 b_d13 b_d15 b_-ce1 b_d14 b_d7 b_d6 a_d1 a_d8 a_d0 a_d10 a_reset a_a5 pwrgood a_d3 a_-cd1 a_d4 a_d11 a_d5 a_d12 a_a10 a_d6 a_d13 a_d7 a_d14 a_-ce1 a_d15 a_-ce2 a_-oe a_a11 a_-iord a_-iowr a_a9 a_a16 a_a21 a_a25 a_a19 a_a22 a_a7 b_a10 a_a24 a_a12 a_a23 a_a15 a_rdy/-ireq a_-we a_a20 a_a8 memcs16* sd4 a_a6 a_-wait a_a3 a_-inpack a_a2 a_a1 a_bvd2/-spkr/-l e a_a0 a_bvd1/-stschg / sa13 sd0 la20 a_a17 a_a18 b_a19 b_d9 b_-cd2 a_a14 a_a13 b_a3 b_-wait b_a22 b_a13 b_a8 b_a17 b_-iowr b_a9 b_-iord b_a11 b_a18 b_a14 b_a12 b_a24 b_a7 b_a25 sd11 irq12/led_out* memw* gnd 200 175 176 177 178 179 1 123 111 pd6722 208-pin mqfp or lqfp +5v isa_vcc b_socket_vcc a_socket_vcc a_gpstb a_a4 b_socket_vcc gnd b_gpstb core_vdd a_socket_vcc a_socket_vcc gnd b_socket_vcc iocs16* la23 b_a23 b_a15
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 15 an asterisk (*) at the end of a pin name indicates an active-low signal for the isa bus or that is a general interface for the pd67xx. pins marked with a dagger ( ? ) in the pin description tables can be switched between cmos and ttl input levels when core_vdd is powered at 5 volts. all other pins use cmos input levels when core_vdd is powered at 5 volts and ttl input levels when powered at 3.3 volts. a pin name ending in bracketed digits separated by a colon [n:n] indicates a multi-pin bus. the pin number (pin number) column indicates the package pin that carries the listed signal. note that multi-pin buses are listed with the first pin number corresponding to the most- significant bit of the bus. for example, pin numbers 123:120, 118, 117, 115, 114, 112, 110, 108:106, 104, 103, 101, and 100 are associated with isa bus address input and data input/ output pins sa[16:0] and indicate that: ? sa16 is pin 123 ? sa15 is pin 122 ? sa0 is pin 100 the quantity (qty.) column indicates the number of pins used (per socket where applicable). the i/o-type code (i/o) column indicates the input and output configurations of the pins on the pd67xx.the possible types are defined below. the power-type code (pwr.) column indicates the output drive power source for an output pin or the pull-up power source for an input pin on the pd67xx. the possible types are defined below. i/o type description i input pin o constant-driven output pin i/o input/output pin o-od open-drain output pin o-ts tristate output pin -pu an internal pull-up resistor is present gnd ground pin pwr power pin power type output or pull-up power source 1 +5v: powered from a 5.0-volt power supply in most systems (see description of +5v pin in table 5 ) 2 a_socket_vcc: powered from the socket a v cc supply connecting to pc card pins 17 and 51 of socket a
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 16 datasheet note: all pin inputs are referenced to core_vdd, independent of their output supply voltage. the drive-type (drive) column describes the output drive-type of the pin (see dc specifications in ? electrical specifications ? on page 101 for more information). note that the drive type listed for an input-only (i) pin is not applicable ( ? ). 3.3 pin descriptions 3 b_socket_vcc: powered from the socket b v cc supply connecting to pc card pins 17 and 51 of socket b 4 isa_vcc: powered from the isa bus power supply 5 core_vdd: usually powered from the lowest available power supply for lowest power consumption, which in most systems is 3.3 volts power type output or pull-up power source table 1. isa bus interface pins (sheet 1 of 4) pin name description pin number qty. i/o pwr. drive pd6710 pd6722 la[23:17] isa bus address input : connect to isa signals la[23:17] or, for systems limited to 1-mbyte address space, tie ale high, ground la[23:20] and connect la[19:17] to isa signals sa[19:17]. 96, 94, 92, 89, 87, 85, 84 157, 155, 153, 151, 149, 147, 146 7i 4 ? sa[16:0] isa bus address input : connect to isa signals sa[16:0]. 123:120, 118, 117, 115, 114, 112, 110, 108:106, 104, 103, 101, 100 184:181, 179, 178, 176, 175, 173, 171, 169:167, 165, 164, 162, 161 17 i 4 ? sd[15:0] isa bus data input/output : these pins are used to transfer data during a memory or i/o cycle. connect to isa signals sd[15:0]. for 8-bit system buses, leave sd[15:8] unconnected. 71, 73 ? 75, 77, 79 ? 81, 140, 139, 137, 136, 134, 132, 130, 129 134 ? 137, 139, 141 ? 143, 200, 199, 197, 196, 194, 193, 190, 189 16 i/o 4 12 ma sbhe* byte high enable : this input is used in conjunction with sa[0] to specify the width and alignment of a data transfer. connect to isa signal sbhe*. for 8-bit system buses, pull up connect to isa_vcc supply. 98 159 1 i 4 ? ior* i/o read : this input indicates that a host i/o read cycle is occurring. connect to isa signal ior*. 124 185 1 i 4 ? iow* i/o write : this input indicates that a host i/o write cycle is occurring. connect to isa signal iow*. 125 186 1 i 4 ?
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 17 memr* memory read : this input indicates that a host memory read cycle is occurring. connect to isa signal memr*. 83 145 1 i 4 ? memw* memory write : this input indicates that a host memory write cycle is occurring. connect to isa signal memw*. 82 144 1 i 4 ? refresh* refresh : this input indicates a memory refresh cycle is occurring and will cause the pd67xx to ignore memory accesses on the bus. connect to isa signal refresh*. 119 180 1 i 4 ? ale address latch enable : a high on this input indicates a valid memory address on the la[23:17] bus lines. connect to isa signal bale. 105 166 1 i 4 ? pwrgood power good : the pd67xx will be reset when the powergood input is low. connect to the powergood signal from the system power supply; or, if not available, connect to inverted resetdrv signal from isa bus. 141 201 1 i 4 ? aen address enable : this is an input from the host cpu bus signal that distinguishes between dma and non-dma bus cycles. this input should be high for a dma cycle and will cause the pd67xx to ignore ior* and iow* except when a pd6722 is configured for dma and its dreq (irq10) and dack* (irq9) signals are active. connect to isa signal aen. when pd67xx is in suspend mode (see ? misc control 2 ? on page 72 ), pull this input high during system power-down for lowest power consumption. 126 187 1 i 4 ? memcs16* memory select 16 : this output is an acknowledge of 16-bit-wide access support and is generated by the pd67xx when a valid 16-bit-word-accessible memory address has been decoded. connect to isa signal memcs16*. 99 160 1 o-od 4 16 ma iocs16* i/o select 16 : this output is an acknowledge for 16-bit-wide access support and is generated by the pd67xx when a valid 16-bit word accessible i/o address has been decoded. connect to isa signal iocs16*. 97 158 1 o-od 4 16 ma iochrdy i/o channel ready : this output is driven low by the pd67xx to lengthen host cycles. connect to the isa bus iochrdy signal. 127 188 1 o-ts 4 16 ma table 1. isa bus interface pins (sheet 2 of 4) pin name description pin number qty. i/o pwr. drive pd6710 pd6722
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 18 datasheet irq[14, 11, 7, 5:3] interrupt request : these outputs indicate programmable interrupt requests generated from any of a number of card actions. although there is no specific mapping requirement for connecting interrupt lines from the pd67xx to the system, a common use is to connect these pins to the corresponding isa signal names in the system. 86, 93, 116, 113, 111, 109 148, 154, 177, 174, 172, 170 6o-ts 42 ma irq9 interrupt request 9 : in default mode this output indicates an interrupt request from one of the cards. when the pd6722 is in dma mode (see misc control 2, bit 6), irq9 becomes an input and is connected to the isa bus dack* line corresponding to the isa bus dreq line that the irq10 pin is connected to. in dma mode this signal is active-low. 138 198 1 i/o-ts 4 2 ma irq10 interrupt request 10: in irq mode this output indicates an interrupt request from one of the cards. when the pd6722 is in dma mode (see misc control 2 , bit 6), irq10 is the dreq to be connected to dreq0, 1, 2, 3, 5, 6, 7 of the isa bus. in dma mode this signal is active-high. 95 156 1 o-ts 4 2 ma irq12/ led_out* interrupt request 12 / led output : in default irq mode this output indicates an interrupt request from one of the cards, and is connected to the isa bus irq12 signal. when the drive led enable bit (see ? bit 4 ? drive led enable ? on page 73 ) is set, this output becomes an open-drain driver for a disk-active led (see ata control register bit 1) or pc card activity led (see extension control 1 register bit 2). 90 152 1 o-ts or o-od 4 12 ma irq15/ ri_out* interrupt request 15 / ring indicate output : in irq mode this output indicates an interrupt request from one of the cards. when the irq15/ri_out* is ri out bit (see ? bit 7 ? irq15 is ri out ? on page 74 ) is set to ? 1 ? , this output is the -ri signal from the corresponding pc card. 88 150 1 o-ts 4 2 ma -intr interrupt : this output indicates a management interrupt. this should be connected to the system processor ? s smi or nmi interrupt input, depending on the type of processor used. 143 203 1 o-ts 4 2 ma zws* zero wait state : this output is connected to the isa zws (0ws) signal. it is driven low by the pd67xx when it is able to complete the current memory access cycle in zero wait states. 131 191 1 o-od 4 16 ma table 1. isa bus interface pins (sheet 3 of 4) pin name description pin number qty. i/o pwr. drive pd6710 pd6722
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 19 spkr_out*/ c_sel speaker out / chip select : this i/o pin can be used as a digital output to a speaker to allow a system to support a pc card ? s - spkr pin for fax/modem/voice and audio. during reset this pin also serves as a chip- configuration input. if the level on this pin is low when pwrgood rises, the pd6710 is configured to support cards as a pc card socket 2 device, and the pd6722 is configured to support cards as pc card socket 2 and socket 3 devices. if the level on this pin is high when pwrgood rises, the pd6710 is configured to support cards as a pc card socket 0 device, and the pd6722 is configured to support cards as pc card socket 0 and socket 1 devices. this pin is internally pulled up during reset so that default configuration of the chip as a socket 0 (and socket 1 for pd6722) is facilitated. adhere to the minimum pulse- width timing specification for pwrgood to allow the internal pull-up to operate and ensure the default configuration. refer to ? bit 6 ? socket index ? on page 41 for more information on chip configuration. after reset operations have completed, this pin defaults to high-impedance, and can then be enabled as a totem-pole speaker output by the setting of a card socket ? s speaker enable bit ( misc control 1 register, bit 4). this output then becomes the negative polarity xor of each socket ? s bvd2/-spkr/-led input that has its speaker enable bit set. for a description of socket index values, refer to table 11 . 142 202 1 i/o- pu 4 12 ma clk clock: this input is connected to the isa bus osc signal. a 14.318-mhz signal is used to derive the internal 25-mhz clock used for all socket timing. alternately, a 25- mhz clock source can be directly connected and the internal synthesizer bypassed. 102 163 1 i 4 ? -vpp_valid in default mode this is a status input that can be used by software as an indication that the v pp power supply is stable. when the pd6722 is in dma mode (see misc control 2, bit 6), this input is connected to the tc (terminal count) signal of the isa bus. in dma mode, this signal is active-high. 431i1 ? isa_vcc system bus v cc : this supply pin can be set to 3.3 or 5.0 v. the isa bus interface pin group (this table) operates at the voltage applied to this pin independent of the voltage applied to other pin groups. 76, 135 138, 195 2 pwr ?? table 1. isa bus interface pins (sheet 4 of 4) pin name description pin number qty. i/o pwr. drive pd6710 pd6722
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 20 datasheet table 2. socket interface pins (sheet 1 of 4) pin name 1 description 2 pin number qty. i/o pwr. drive pd6710 pd6722 socket a socket b -reg register access: in memory card interface mode, this output chooses between attribute and common memory. in i/o card interface mode for non-dma transfers, this signal is active (low). for dma cycles on the pd6722 to a dma-capable card, -reg is inactive during i/o cycles to indicate a dma cycle to or from the pc card. in ata mode, this signal is always inactive. 8 8 71 1 o-ts 2 or 3 2 ma a[25:0] pc card socket address outputs. 48, 46, 44, 42, 40, 38, 36, 34, 32, 41, 43, 35, 33, 45, 27, 24, 29, 31, 47, 49, 50, 53, 56, 58, 59, 61 48, 46, 44, 42, 40, 38, 36, 34, 32, 41, 43, 35, 33, 45, 25, 21, 28, 30, 47, 49, 50, 53, 55, 57, 58, 60 110, 108, 106, 104, 102, 100, 98, 96, 94, 103, 105, 97, 95, 107, 89, 85, 91, 93, 109, 112, 113, 115, 118, 120, 121, 123 26 o-ts 2 or 3 2 ma d[15:0] ? pc card socket data i/o signals. 23, 21, 17, 14, 12, 68, 66, 64, 19, 15, 13, 11, 9, 67, 65, 63 20, 18, 16, 14, 12, 67, 65, 63, 17, 15, 13, 11, 9, 66, 64, 62 84, 82, 80, 77, 75, 130, 128, 126, 81, 78, 76, 74, 72, 129, 127, 125 16 i/o 2 or 3 2 ma -oe output enable : for non-dma transfers, this output goes active (low) to indicate a memory read from the socket. during a dma write (when -iord is active) this output goes low if the isa output tc is active (high), indicating to the card that the system ? s terminal count signal is active. during dma reads (when -iowr is active), this output remains high. 26 23 87 1 o-ts 2 or 3 2 ma 1. 1 to differentiate the sockets, all pd6722 pin names have either a_ or b_ prepended to the pin names indicated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see table 17 on page 88 .
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 21 -we write enable : for non-dma transfers, this signal goes active (low) to indicate a memory write to the socket. during a dma read (when -iowr is active), this signal goes low if the isa output tc is active (high), indicating to the card that the system ? s terminal count signal is active. during dma writes (when -iord is active), this output remains high. 37 37 99 1 o-ts 2 or 3 2 ma -iord i/o read : this output is driven low for i/ o reads from the socket. 28 26 90 1 o-ts 2 or 3 2 ma -iowr i/o write : this output is driven low for i/ o writes to the socket. 30 29 92 1 o-ts 2 or 3 2 ma wp/ -iois16 ? write protect / i/o is 16-bit : in memory card interface mode (interrupt and general control register, bit 5 is equal to ? 0 ? ), this input is the status of the pc card write protect switch. in i/o card interface mode, a low on this input indicates that the i/o address being accessed is capable of 16-bit operation. in dma mode, this pin can be programmed as the -dreq input from a dma-capable pc card. 69 68 131 1 i-pu 2 or 3 ? -inpack ? input acknowledge : this input indicates to the pd67xx that the pc card supports i/o access at the current address. a pc card activates this input during iord cycles to which the card can respond. in dma mode, this pin can be programmed as the -dreq input from a dma-capable pc card. 57 56 119 1 i-pu 2 or 3 ? rdy/ -ireq ? ready / interrupt request : in memory card interface mode, this input is readable as the status of bit 5 of the interface status register, which is used by a pc card to signal system software of its ready or busy state. in i/o card interface mode, this active- low input indicates an interrupt request. 39 39 101 1 i-pu 2 or 3 ? -wait ? wait : this input indicates to the pd67xx that the current card access cycle is to be extended until this signal becomes inactive (high). 55 54 116 1 i-pu 2 or 3 ? table 2. socket interface pins (sheet 2 of 4) pin name 1 description 2 pin number qty. i/o pwr. drive pd6710 pd6722 socket a socket b 1. 1 to differentiate the sockets, all pd6722 pin names have either a_ or b_ prepended to the pin names indicated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see table 17 on page 88 .
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 22 datasheet -cd[2:1] card detect : these inputs indicate to the pd67xx the presence of a card in the socket. they are pulled high internally in the chip. 70, 10 69, 10 132, 73 2 i-pu 1 ? -ce[2:1] card enable : these outputs are driven low by the pd67xx during card access cycles to control byte/word card access. -ce1 enables even-numbered address bytes and -ce2 enables odd- numbered address bytes. when configured for 8-bit cards, only -ce1 will be active and a0 will be set to ? 1 ? for odd-byte accesses. 25, 22 22, 19 86, 83 2 o-ts 2 or 3 2 ma reset reset : this output will be high to reset the card and low for normal operation. to reduce power consumption of idle cards and to prevent reset glitches to a card, this signal is high-impedance unless a card is fully seated in the socket and card interface signals are enabled. 51 51 114 1 o-ts 2 or 3 2 ma table 2. socket interface pins (sheet 3 of 4) pin name 1 description 2 pin number qty. i/o pwr. drive pd6710 pd6722 socket a socket b 1. 1 to differentiate the sockets, all pd6722 pin names have either a_ or b_ prepended to the pin names indicated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see table 17 on page 88 .
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 23 bvd2/ -spkr/ -led ? battery voltage detect 2 / speaker / led : in memory card interface mode, this input serves as the bvd2 or battery warning status input. in i/o card interface mode, this input can be configured as a card ? s -spkr binary audio input. for disk-drive support, bvd2/-spkr/-led can also be configured as a drive-status led input. in dma mode, this pin can be programmed as the -dreq input from a dma-capable pc card. 60 59 122 1 i-pu 2 or 3 ? bvd1/ -stschg/ -ri ? battery voltage detect 1 / status change / ring indicate : in memory card interface mode, this input serves as bvd1 (battery dead status) input. in i/o card interface mode, this input is the -stschg input, which indicates to the pd67xx that the card ? s internal status has changed. in i/o card interface mode, this input can alternately be used as -ri ring indicate when irq15/ri_out* is configured for ri out (see ? bit 7 ? irq15 is ri out ? on page 74 ). 62 61 124 1 i-pu 2 or 3 ? socket_ vcc connect these pins to the v cc supply of the socket (pins 17 and 51 of the respective pc card socket). these pins can thus be 0, 3.3, or 5 v, depending on card presence, card type, and system configuration. the socket interface outputs (listed in this table) will operate at the voltage applied to these pins, independent of the voltage applied to other pd67xx pin groups. 18, 52 24, 52 88, 117 2 pwr ?? table 2. socket interface pins (sheet 4 of 4) pin name 1 description 2 pin number qty. i/o pwr. drive pd6710 pd6722 socket a socket b 1. 1 to differentiate the sockets, all pd6722 pin names have either a_ or b_ prepended to the pin names indicated. for example, a_a[25:0] and b_a[25:0] are the independent address buses to the sockets. 2. 2 when a socket is configured as an ata drive interface, socket interface pin functions change. see table 17 on page 88 .
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 24 datasheet table 3. general-purpose strobe / voltage sense pins pin name description pin number qty. i/o pwr. drive pd6710 pd6722 socket a socket b gpstb general-purpose strobe: connect a_gpstb to pin 43 and b_gpstb to pin 57 on pc card socket. this pin can be used with external logic to sense pins vs1 and vs2 of the socket. it is only available on the pd6722. 1, 2 ? 671 i-pu/ o- oc 12 ma 5v_det this status input is used to detect 5 v/ 3.3 v on pcmcia pin 57. 7 ?? 1i-pu 1 n/a 1. general-purpose strobe controlled by ? socket a ? (index 2eh/2fh) extension control 2 register at extended index 0bh. 2. general-purpose strobe controlled by ? socket b ? (index 6eh/6fh) extension control 2 register at extended index 0bh. table 4. power control pins pin name description pin number qty . i/o pwr. drive pd6710 pd6722 socket a socket b vpp_vcc this output is used to enable the socket v cc supply onto the v pp pin. this pin is mutually exclusive with vpp_pgm. 3 2 205 1 o 1 12 ma vpp_pgm this output is used to enable the programming voltage supply onto the v pp pin. this pin is mutually exclusive with vpp_vcc. 2 1 204 1 o 1 12 ma -vcc_3 this output is used to enable a 3.3v supply onto the v dd socket. this pin is mutually exclusive with -vcc_5. 5 4 206 1 o 1 12 ma -vcc_5 this output is used to enable a 5v supply onto the v dd socket. this pin is mutually exclusive with -vcc_3. 6 5 207 1 o 1 12 ma
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 25 table 6 below summarizes the pin usage. 3.4 power-on configuration summary on the rising edge of pwrgood, the pd67xx latches the configuration pin spkr_out*/ c_sel to determine which sockets are addressed by this device. a ? 1 ? on the spkr_out*/ c_sel pin will cause the device to address socket 0 (and socket 1 for the pd6722). a ? 0 ? on this pin will cause the device to address socket 2 (and socket 3 for the pd6722). table 5. power and ground pins pin name description pin number qty. i/o pwr. drive pd6710 pd6722 +5v this pin is connected to the system ? s 5-volt power supply. in systems where 5 volts is not available, this pin can be connected to the system ? s 3.3-volt supply (but 5-volt-only pc cards will not be supported). 1 208 1 pwr ?? core_vdd this pin provides power to the core circuitry of the pd67xx. it can be connected to either a 3.3- or 5-volt power supply, independent of the operating voltage of other interfaces. for power conservation on a system with a 3.3-volt supply available, this pin should be connected to the 3.3-volt supply even if there is no intention of operating other interfaces on the device at less than 5 volts. 16, 91 27, 133 2 pwr ?? gnd all ground pins should be connected to system ground. 20, 54, 72, 78, 128, 133 31, 70, 79, 111, 140, 192 6gnd ?? table 6. pin usage summary pin group pin quantity pd6710 pd6722 isa bus interface pins 69 69 socket interface pins 60 120 general-purpose strobe pins 0 2 voltage sense pins 1 0 n/c 1 0 power control pins 4 8 power and ground pins 9 9 total: 144 208
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 26 datasheet table 7. chip configuration at power-up for socket support spkr_out*/c_sel level at rising edge of pwrgood pd6710 pd6722 socket interface support socket a interface support socket b interface support high pc card socket 0 3e0 index 00h ? 3fh pc card socket 0 3e0 index 00h ? 3fh pc card socket 1 3e0 index 40h ? 7fh low pc card socket 2 3e0 index 80h ? bfh pc card socket 2 3e0 index 80h ? bfh pc card socket 3 3e0 index c0h ? ffh
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 27 4.0 introduction 4.1 system architecture this section describes pc card basics, windowing, interrupts, pd67xx power management, socket power management, write fifo, bus sizing, programmable pc card timing, and ata and dma mode operation. 4.1.1 pc card basics pcmcia is an abbreviation for personal computer memory card international association. pc card standard is a standard for using memory and i/o devices as insertable, exchangeable peripherals for pcs (personal computers) and handheld computers. for simpler end-user and vendor implementation of the standard, systems employing pc card standard should also be backward-compatible with industry-standard pc addressing. note: the pd67xx is backward-compatible with pcmcia standards 1.0, 2.0, 2.01, and 2.1. the pd67xx is also compatible with jeida 4.1 and its earlier standards corresponding with the pcmcia standards above. the memory information for memory-type pc cards must be mapped into the system memory address space. this is accomplished with a ? windowing ? technique that is similar to expanded memory schemes already used in pc systems (for example, lim 4.0 memory manager). pc cards can have attribute and common memory. attribute memory is used to indicate to host software the capabilities of the pc card, and it allows host software to change the configuration of the card. common memory can be used by host software for any purpose (such as flash file system, system memory, and floppy emulation). i/o-type pc cards, such as modem network cards, should also be directly addressable, as if the cards were i/o devices plugged into the system bus. for example, it would be highly desirable to have a pc card modem accessible to standard communications software as if it were at a com port. for com1, this would require that the modem be accessed at system i/o address 3f8h ? 3ffh. the method of mapping a pc card i/o address into anticipated areas of isa i/o space is done similarly to memory windowing. i/o-type pc cards usually have interrupts that need to be serviced by host software. for the example of a modem card accessed as if at com1, software would expect the modem to generate interrupts on the irq4 line. to be sure all interrupts are routed as expected, the pd67xx can steer the interrupt from the pc card to one of several standard pc interrupts (see ? interrupts ? on page 30 and the ? interrupt and general control ? on page 51 ). 4.1.2 pd67xx windowing capabilities for full compatibility with existing software, and to ensure compatibility with future memory cards and software, the pd67xx provides five programmable memory windows per socket and two programmable i/o windows per socket. these windows can be used by an inserted pc card to access isa memory and i/o space.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 28 datasheet having five memory windows per socket allows a memory-type card to be accessed through four memory windows programmed for common memory access (allowing pc-type expanded- memory-style management), leaving the fifth memory window available to be programmed to access the card ? s attribute memory without disrupting the common memory in use. each of the five memory windows has several programming options, including: each of the two i/o windows has several programming options, including: caution: the windows of the pd67xx should never be allowed to overlap with each other or the other devices in the system. this would cause collisions in the iocs16*, memcs16*, iochrdy, and sd[15:0] signals, resulting in erratic behavior. memory window option description enabled each of the five memory windows can be individually enabled. disabled windows are not responded to. start address the starting address of the window is programmable on 4-kbyte boundaries starting at 64 kbytes (1000h) with a maximum address of 16 mbyte. end address the ending address of the window is programmable on 4-kbyte boundaries starting at 64 kbytes (1000h) with a maximum address of 16 mbyte. only memory accesses between the starting and ending address are responded to. offset address the offset address is added to the isa address to determine the address for accessing the pc card. this allows the addresses in the pc card address space to be different from the isa address space. data size the size of accesses can be set manually to either 8 or 16 bits. timing the timing of accesses (setup/command/recovery) can be set by either of two timing register sets: timer set 0 or timer set 1. register access setting the -reg pin can be enabled on a per-window basis so that any of the windows can be used for accessing attribute memory. write protect if the window is programmed to be write-protected, then writes to the memory window are ignored (reads are still performed normally). i/o window option description enabled each of the two i/o windows can be individually enabled. start address the starting address of the window is programmable on single-byte boundaries from 0 to 64 kbytes. end address the ending address of the window is also programmable on single-byte boundaries from 0 to 64 kbytes. offset address the offset address is added to the isa address to determine the address for accessing the pc card. auto size the size of accesses can be set automatically, based on the pc card -iois16 signal. data size the size of accesses can be set manually to either 8 or 16 bits, overriding the auto size option. timing the timing of accesses (setup/command/recovery) can be set by either of two timing register sets: timer set 0 or timer set 1.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 29 figure 5. memory window organization figure 6. i/o window organization isa memory address space pc card memory address space common memory attribute memory card memory map system memory map system memory map end address registers start address registers offset address registers card memory window memory window 16 mbytes 64 mbytes note: isa memory window can map to either common or attribute pc card memory. first 64 kbytes ? ? ? ? ? not usable in most isa systems isa i/o address space pc card i/o address space system i/o map system i/o map end address registers start address registers i/o window card i/o window 64 mbytes 64 kbytes card i/o map offset address registers
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 30 datasheet 4.1.3 pd67xx functional blocks 4.1.4 interrupts the pd67xx provides ten interrupt pins that are labeled with names suggesting their mapping in the system, though there are no hard requirements specifying the exact mapping. typically, all ten interrupt pins should be connected to system interrupt signals to allow maximum flexibility in programming interrupt routing from the pd67xx. classes of interrupts the pd67xx supports two classes of interrupts: socket or card interrupts initiated by the pc card activating its rdy/-ireq signal management interrupts triggered by changes in pc card status, including: ? card insertion or removal ? battery warning indicator (bvd2) change on a memory-type card ? battery dead indicator (bvd1) or i/o-type card status change (-stschg) ? ready (rdy) status change on a memory-type card either class of interrupts can be routed to any of the ten interrupt pins on the pd67xx. figure 7. functional block diagram operation registers mapper and offset socket socket write fifo power control interrupt control synthe- bus interface unit sizer per chip per socket control data address v cc control v pp control control address data clock intr irqs bus control timing control -wait wp/-iois16 cd1, cd2 rdy/-ireq bvd, -stschg
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 31 connection of interrupt pins irq interrupts in pc-compatible systems are not generally shared by hardware. therefore, each device in the system using irq interrupts must have a unique interrupt line. additionally, many software applications assume that certain i/o devices use specific irq signals. to allow pc cards with differing i/o functionalities to be connected to appropriate nonconflicting irq locations, the pd67xx can steer the interrupt signal from a pc card to any one of the ten different hardware interrupt lines. for some i/o-type cards, software is written so that irq interrupts can be shared. the pd67xx contains unique logic that allows irq interrupts to be shared under software control. this is accomplished by programming the pd67xx to alternately pulse and then three-state the desired interrupt pin, which has been programmed as an irq output. this unique irq interrupt sharing technique can be controlled through software so that systems incapable of irq sharing have no loss of functionality. 4.1.5 alternate functions of interrupt pins the pd67xx has two interrupt pins that can be programmed for alternate functions: irq12/ led_out* and irq15/ri_out*. in addition, the pd6722 allows irq9 and irq10 to be programmed for system dma transfer handshake functions. 4.1.5.1 irq12 as led_out* driver if a disk-activity or card-cycle-activity indicator is desired, irq12/led_out* can be programmed as an open-collector led driver, capable of driving most common leds. there is no specific bit that programs the irq12 pin to become an led driver; instead, whenever a socket interface is programmed to support a drive status led input or is programmed to show card activity on the led (as described below), the irq12 pin becomes reconfigured as an open- collector led driver. the extension control 1 register ? s led activity enable bit (extended index 03h bit 2) is used to enable the led being used to show card activity. when this bit is set, any type of read or write cycles to the respective socket cause the irq12/led_out* signal to be driven low for the duration of the card activity. the drive led enable bit ( misc control 2 register bit 4) is used to enable the bvd2/-spkr/- led input from an i/o-interfaced card to be interpreted as a drive led input, where an open- collector signal driven low on this input will cause the irq12/led_out* open-collector output to go low. any combination of settings of led activity enable and drive led enable bits can be used on each socket, with each type of activity being able to separately cause the led to be illuminated. status from non-present or non-activated cards is automatically masked off from causing the irq12/led_out* signal to be driven low. 4.1.5.2 irq15 as ri_out* if the capability to ? wake up ? a system on an incoming phone call to a pc card modem is desired, it may be necessary in some systems to use a dedicated wakeup signal to the system ? s smi or nmi controller to facilitate this instead of using the normal interrupt connections. if this is the case, the irq15 connection can be reprogrammed to pass through a qualified version of an i/o interfaced card ? s -ri signal.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 32 datasheet irq15/ri_out* is programmed as ri_out* by programming the irq15 is ri out bit ( misc control 2 register 1eh bit 7) to ? 1 ? . then if a particular socket supporting a modem is to have its bvd1/-stschg/-ri pin passed to the irq15/ri_out* pin, that socket ? s ring indicate enable bit ( interrupt and general control register 03h bit 7) should be set to ? 1 ? . when the pd67xx is configured this way, a low level at the bvd1/-stschg/-ri pin on an i/o interfaced pc card will cause the irq15/ri_out* signal to become active-low (because it is intended to be connected to an smi* or nmi* input on the system processor or core logic). to prevent multiple smi or nmi interrupts from occurring on one ring condition, the irq15/ ri_out* pin remains low until isa bus activity resumes, indicated by the resumption of isa bus memory or i/o reads or writes. 4.1.5.3 irq9 as dack* and irq10 as drq when a pd6722 is to be used for dma support, irq9 is programmed as a dack* input from an isa bus dack* signal selected by the system designer. similarly, irq10 is programmed as an active-high drq output to the isa bus and should be connected to the system bus drq signal corresponding to that used for dack*. irq9 and irq10 are thus redefined for dma cycle support by the setting of the dma system bit ( misc control 2 register 1eh, bit 6) to ? 1 ? . setting the dma system bit redefines these isa interface signals but does not cause dma to a card to be enabled. 4.1.6 general-purpose strobe feature the pd6722 has capability to use two pins as general-purpose strobes. this is a feature that causes a pin programmed as a general-purpose strobe to appear in software as an extended register in the pd6722 register set, while in reality accesses to this extended register cause the general-purpose strobe pin to go active during the register access. the strobe can be programmed to activate on reads or writes to this virtual extended register, allowing straightforward single-chip implementation of an 8-bit general purpose read or write port. ? using gpstb pins for external port control (pd6722 only) ? on page 91 provides detailed information on how this port can be used. 4.1.7 voltage sense pins the pd6710 provides a single pin to detect 5 v or 3.3 v on pin 57 of the pc card. the pd6722 can be simply configured for dual-socket vs1 and vs2 detection with an external read port consisting of half of a ? 244 buffer or other similar device, enabled by the b_gpstb pin programmed as a read port. ? vs1# and vs2# voltage detection ? on page 95 provides detailed information on the programming model for vs1 and vs2 detection and how connections are made to achieve this functionality. 4.1.8 pd67xx power management to provide the longest possible battery life, the pd67xx provides many power management features, including low-power dynamic mode, suspend mode, and control of pc card socket power.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 33 low-power dynamic mode is transparent to the isa bus. after reset, the pd67xx is configured for low-power dynamic mode. this mode can be turned off by setting misc control 2 register, bit 1 to ? 0 ? . when in low-power dynamic mode, periods of inactivity (no activity on the pc card bus and system accesses to chip registers or inserted cards are no longer being performed) cause the pd67xx to enter a low-power state where the clock is turned off to most of the chip and the pc card address and data lines are set to a static value. v cc and v pp power to the card is left unchanged. when there is activity present on the pc card bus, or the system accesses pd67xx registers, or pc cards are inserted or removed from the socket, the pd67xx enters its active state, services the transaction, and then returns to its low-power state. a suspend mode can also be programmed. the pd67xx suspend mode is the chip ? s lowest software-controlled power mode. the pd67xx is put into suspend mode by setting the misc control 2 register, bit 2 to ? 1 ? . in suspend mode, all the internal clocks are turned off, and only read/write access to the index register and write access to the misc control 2 register is supported. all accesses to the pc cards are ignored when in suspend mode. v cc and v pp power to the card is left unchanged (the system power management software is responsible for turning off power to the socket and entering suspend mode). interrupts and ring indicate signals are passed through to the system bus when in suspend mode. to exit suspend mode, the misc control 2 register bit 2 must be reset to ? 0 ? . it requires 50 ms for the pd67xx to restart the internal clock synthesizer and become active again. in addition to the software suspend, if the system hold ? s the aen signal of the pd67xx high, a hardware-assisted super-suspend mode occurs where isa inputs to the chip are internally shut off. internal in the pd67xx, the isa inputs are ignored and floating conditions on the isa bus will not cause high current flow in the pd67xx isa input receivers. since the isa bus inputs to the core logic of the pd67xx are also not toggling when aen is set high, power consumption is further reduced. interrupts and ring indicate signals are passed through to the system bus when in super- suspend mode the pd67xx power can be further managed by controlling socket power as outlined in ? socket power management features ? on page 34 . socket power can be turned on and off through software or automatically when cards are inserted or removed. the pd67xx provides six pins per socket for controlling external logic to switch v cc and v pp voltages on and off and for sensing a card ? s operating voltage range. cards can be turned off when not in use.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 34 datasheet 4.1.9 socket power management features card removal when a card is removed from a socket, the pd67xx by default automatically disables the v cc and v pp supplies to the socket. if extension control 1 register bit 1 is ? 0 ? , card power is prevented from being automatically disabled when a card is removed. the pd67xx can also be configured to have management interrupts notify software of card removal. card insertion power to the socket is off at reset and whenever there is no card in a socket. when a card is detected (card detect input pins, -cd1 and -cd2, to the pd67xx become asserted low), two independent actions can be programmed to occur. if the pd67xx has been set for automatic power-on ( power control register bits 4 and 5 are both ? 1 ? ), the pd67xx automatically enables the socket v cc supply (and, if so programmed, the v pp supply). if the pd67xx has been programmed to cause management interrupts for card-detection events, assertion of -cd1 and -cd2 to the pd67xx causes a management interrupt to inform system software that a card was inserted. in the case of manual power detection ( power control register table 8. pd67xx power-management modes mode name pwrgood level aen misc control 2 register functionality typical power consumption (core_vdd = 3.3 v, isa_vcc, socket_vcc, and +5v = 5.0 v) suspend mode (bit 2) low-power dynamic mode (bit 1) low-power dynamic (default) high normal 0 1 full functionality < 45 mw high activity, 9 ? 14 mw normal system activity normal high normal 0 0 full functionality < 85 mw high activity, 18 mw normal system activity suspend (software controlled) high normal 1 ? 8-bit access to misc control 2 register. no other register access. no card in socket(s). < 2 mw super-suspend (hardware controlled) high static high 1 ? no register access. no card in socket(s). system bus signals disabled (clock off). < 1 mw reset low 1 ?? ? no register access. no card in socket(s). system bus signals disabled. 9 ? 14 mw 1. ior*, iow*, memr*, and memw* must be held high when pwrgood is low to prevent manufacturing test mode outputs from driving the system data bus
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 35 bit 5 is ? 0 ? ), system software can determine the card ? s operating voltage range and then power-up the socket and initialize the card (or simply initialize the card if programmed for automatic power- on ( power control register bit 5 is ? 1 ? and extension control 1 register bit 1 is ? 1 ? )). 4.1.10 write fifo to increase performance when writing to pc cards, two, independent, four-word-deep write fifos are used. writes to pc cards will complete without wait states until the fifo is full. register states should not be changed until the write fifo is empty. 4.1.11 bus sizing the pd67xx incorporates logic to automatically detect its connection to 8- or 16-bit buses. this is accomplished by sensing sbhe* input activity. if the sbhe* pin is always high (that is, tied to isa_vcc), the pd67xx operates in 8-bit mode where all transfers occur on the lower data bus, bits 7:0. any occurrence of the sbhe* going low triggers the pd67xx to operate thereafter as a 16-bit device. 16-bit operation of the pd67xx is properly triggered when the sbhe* input is connected to the system ? s sbhe* signal. when the pd67xx is operating in 16-bit mode, all isa bus transactions are 16-bit whenever possible, even if installed pc cards only support 8-bit transfers. in 16-bit mode, the signals sbhe* and sa0 are used to specify the width of the data transfer and the location of data on the bus (which byte lane has the data) during 8-bit transfers. the possible combinations for sbhe* and sa0 are shown in table 9 and table 10 . typically, there are three types of data transfers to and from the pd67xx: 16-bit transfer from 16-bit processor ? the cpu puts the address on the bus. then the pd67xx identifies the address on the bus as either an 8- or 16-bit transfer. if the transfer is identified as 16-bit, the host acknowledges with the appropriate signal, either memcs16* or iocs16*. data is transferred to/from the data bus as a word on both byte lanes. 8-bit transfer from 16-bit processor ? the cpu puts the address on the bus. then the pd67xx identifies the address on the bus as either an 8- or 16-bit transfer. in this case, the transfer is identified as an 8-bit transfer. the host queries sa0 and sbhe* to determine the table 9. 16-bit mode operation 16-bit mode transfer types sbhe* sa0 word 0 0 upper byte/odd address 0 1 low byte/even address 1 0 not valid 1 1 table 10. 8-bit mode operation 8-bit mode transfer types 1 sa0 even address 0 odd address 1 1. the sbhe* signal is pulled up. if the sbhe* signal remains high, thepd67xx causes all transfers to occur on d[7:0] only
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 36 datasheet byte lane on which the transfer is to occur. the data is transferred to/from the data bus (see table 9 ). 8-bit transfer from 8-bit processor ? the cpu puts the address on the bus. the host determines that it will be an 8-bit transfer since the sbhe* signal has been tied high. the pd67xx queries sa0 to determine if the byte is odd/even. the data is transferred to/from the data bus (d[7:0]). 4.1.12 programmable pc card timing the setup, command, and recovery time for the pc card bus is programmable (see ? timing registers ? on page 84 ). the pd67xx can be programmed to match the timing requirements of any pc card. there are two sets of timing registers, timer set 0 and timer set 1, that can be selected on a per-window basis for both i/o and memory windows. to be compatible with the 82365sl, the two timing sets are programmed at the rising edge of pwrgood to include normal-wait and one-wait-state timing. 4.1.12.1 ata mode operation the pd67xx supports direct connection to at-attached-interface hard drives. ata drives use an interface very similar to the ide interface found on many popular portable computers. in this mode, the address and data conflict with the floppy drive is handled automatically. see ? ata m o d e operation ? on page 88 for more information. 4.1.13 dma mode operation for the pd6722 a slave mode direct memory access (dma) feature exists in the pd6722. to use dma mode, the interrupt and general control register, bit 5 must be set to ? 1 ? to operate the pc card in i/o card interface mode. pc card interface dma handshake signal options must also be selected. refer to the description of the ? extension control 1 (pd6722 only, formerly dma control) ? on page 78 as well as ? dma operation (pd6722 only) ? on page 97 . 4.1.14 selective data drive for i/o windows the pd67xx can be programmed to drive only some of the isa bus data pins on reads from i/o windows. this reduces data contention for i/o addresses that include more than one peripheral. in the standard ibm ? pc at, i/o map, floppy disk, and hard disk share address 3f7h. the floppy disk drives isa-data-bus bit 7 on a read from 3f7h, and the hard disk drives bits 6:0. to allow both floppy disk controllers on the motherboard and hard disks on the pc card bus (or vice versa) to coexist, the pd67xx can be programmed through use of its data mask registers to disable bit 7 on i/o reads at addresses 3f7h and 377h. this is done by programming up i/o windows to these addresses as part of the task of configuring a socket for ata drive support (see ? extended data ? on page 77 ). alternately, all bits except bit 7 can also be disabled to allow the opposite case. 4.2 host access to registers the pd67xx registers are accessed through an 8-bit indexing mechanism. an index register scheme allows a large number of internal registers to be accessed by the cpu using only two i/o addresses.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 37 the index register (see ? operation registers ? on page 41 ) is used to specify which of the internal registers the cpu will access next. the value in the index register is called the register index. this number specifies a unique internal register. the data register is used by the cpu to read and write the internal register specified by the index register. double-indexed registers the pd67xx has extension registers that add to the functionality of the 82365sl-compatible register set. within the extension registers is an extended index register and extended data register that provide access to more registers. the registers accessed through extended index and extended data are thus double indexed. the example below shows how to access the extension control 1 register, one of the double-indexed registers. ;write to extension control 1 register example ;constants section extended_index equ 2eh index_reg equ 2fh ext_cntrl_1 equ 03h pd67xx_index equ 3e0h ;code section mov dx, pd67xx_index mov al, extended_index mov ah, ext_cntrl_1 figure 8. indexed 8-bit register structure figure 9. indexed 8-bit register example 00h 01h 02h feh ffh 3e1h 3e0h internal registers register indexes i/o addresses data index high byte low byte the following code segment demonstrates use of an indexed 8-bit register: mov dx, 3e0h mov al, 02h mov ah, 3ch out dx, ax 02h 3e1h 3e0h internal registers register indexes i/o addresses 3ch 02h 3ch ah al
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 38 datasheet out dx, ax mov al, index_reg mov ah, user_data ;desired data to be out dx, ax ;written to ;extended index 03h ;read from extension control 1 register example ;code section mov dx, pd67xx_index mov al, extended_index mov ah, ext_cntrl_1 out dx, ax mov al, index_reg out dx, al inc dx ;al has extended in al, dx ;index 03h data 4.3 power-on setup following reset, the pd67xx must be configured by host software. the host software ? s setup procedure is different depending on its pc system configuration, in particular, the power supply arrangement. the application of the reset signal (see table 2 on page 20 ) on power-up causes initialization of all the pd67xx register bits and fields to their reset values. not all registers have reset values; only registers with bits and fields specified to have reset values are initialized. one bit, which is loaded on hardware reset from the spkr_out*/c_sel pin (see table 1 on page 16 ), is used to determine the socket to which the pd67xx will respond.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 39 5.0 register description conventions register headings the description of each register starts with a header containing the following information: special function bits following is a description of bits with special functions: header field description register name indicates the register name. index 1 the index value through which an internal register in an indexed register set is accessed. register per indicates whether the register affects both sockets, marked chip , or an individual socket, marked socket . if socket is indicated, there are two registers being described, each with a separate index value (one for each socket, a and b). a register compatibility type indicates whether the register is 82365sl- compatible, marked 365 or a register extension, marked ext . 1. when the register is socket-specific, the index value given in the register heading is for socket a only. for the socket b register on the pd6722, add 40h to the index value of the socket a register. bit type description reserved these bits are reserved and should not be changed. compatibility bit these bits have no function on the pd67xx, but are included for compatibility with the 82365sl register set. 0 or 1 these read-only bits are forced to either ? 0 ? or ? 1 ? at reset and cannot be changed. scratchpad bit these read/write bits are available for use as bits of memory.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 40 datasheet bit naming conventions the following keywords are used within bit and field names: read/write convention keyword description enable indicates that the function described in the rest of the bit name is active when the bit is ? 1 ? . disable indicates that the function described in the rest of the bit name is active when the bit is ? 0 ? . mode indicates that the function of the bit alters the interpretation of the values in other registers. input indicates a bit or field that is read from a pin. output indicates a bit or field that is driven to a pin. select indicates that the bit or field selects between multiple alternatives. fields that contain select in their names have an indirect mapping between the value of the field and the effect. status indicates one of two types of bits: either read- only bits used by the pd67xx to report information to the system, or bits set by the pd67xx in response to an event, and can also be cleared by the system. the system cannot directly cause a status bit to become ? 1 ? . value indicates that the bit or field value is used as a number. bit access description rw:n bit is read/write and resets to value n when pwrgood is cycled. r bit is read-only and setting is determined by conditions noted. set this bit to ? 0 ? , or echo back value read. r:n bit is read-only and resets to value n when pwrgood is cycled. set this bit to ? 0 ? , or echo back value read. r:n w:m bit is read/write and resets to value n when pwrgood is cycled. set this bit to value m only.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 41 6.0 operation registers the pd67xx internal registers are accessed through a pair of operation registers ? an index register and a data register. the index register is accessed at address 03e0h, and the data register is accessed at 03e1h. 6.1 index the data register is accessed at 03e1h. bits 5:0 ? register index these bits determine which of the 64 possible socket-specific registers will be accessed when the data register is next accessed by the processor. note that some values of the register index field are reserved (see table 11 on page 42 ). bit 6 ? socket index this bit determines which set of socket-specific registers is currently selected. when this bit is ? 0 ? , a socket a register is selected. when this bit is ? 1 ? , a socket b register is selected. note that the pd6710 supports one socket, and the pd6722 supports two sockets. bit 7 ? device index in systems where two pd67xxs are used, this bit differentiates between them. the index register value determines which internal register should be accessed (read or written) in response to each cpu access of the data register. each of the possible pc card sockets is allocated 64 of the 256 locations in the internal register index space register name: index index: n/a register per: chip register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 device index socket index register index rw:0 rw:0 rw:000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 42 datasheet . when viewed as a 8-bit value, the contents of the index register completely specify a single internal-register byte. for example, when the value of this register is in the range 00h ? 3fh, a socket a register is selected (socket index bit is ? 0 ? ), and when the value of this register is in the range 40h ? 7fh, a socket b register is selected (socket index bit is ? 1 ? ). this register only reads back for device 0. device 1 will read back only the upper data byte when 16-bit reads occur at 3e0h. the internal register that is accessed when the cpu reads or writes the data register is determined by the current value of the index register, as follows: figure 10. device/socket/register index space socket b registers socket a registers 00h 3fh 40h 80h 7fh ffh socket d registers socket c registers possible with two pd67xxs table 11. index registers (sheet 1 of 3) register name index value chapter page number socket a socket b 1 chip revision 00h 2 ? chip control registers ? on page 46 46 interface status 01h 41h 47 power control 02h 42h 48 interrupt and general control 03h 43h 51 card status change 04h 44h 52 management interrupt configuration 05h 45h 54 mapping enable 06h 46h 55 i/o window control 07h 47h ? i/o window mapping registers ? on page 58 58 system i/o map 0 start address low 08h 48h 59 system i/o map 0 start address high 09h 49h 60 system i/o map 0 end address low 0ah 4ah 60 system i/o map 0 end address high 0bh 4bh 61 system i/o map 1 start address low 0ch 4ch 59 system i/o map 1 start address high 0dh 4dh 60 system i/o map 1 end address low 0eh 4eh 60 system i/o map 1 end address high 0fh 4fh 61 1. socket b is available on the dual-socket pd6722. 2. this register affects both sockets (it is not specific to either socket). 3. these registers are not available on the pd6710.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 43 system memory map 0 start address low 10h 50h ? memory window mapping registers ? on page 64 64 system memory map 0 start address high 11h 51h 65 system memory map 0 end address low 12h 52h 66 system memory map 0 end address high 13h 53h 66 card memory map 0 offset address low 14h 54h 67 card memory map 0 offset address high 15h 55h 68 misc control 1 16h 56h ? extension registers ? on page 70 70 fifo control 17h 57h 72 system memory map 1 start address low 18h 58h ? memory window mapping registers ? on page 64 64 system memory map 1 start address high 19h 59h 65 system memory map 1 end address low 1ah 5ah 66 system memory map 1 end address high 1bh 5bh ? memory window mapping registers ? on page 64 61 card memory map 1 offset address low 1ch 5ch 67 card memory map 1 offset address high 1dh 5dh 68 misc control 2 1eh 2 ? extension registers ? on page 70 72 chip information 1fh 2 74 system memory map 2 start address low 20h 60h ? memory window mapping registers ? on page 64 64 system memory map 2 start address high 21h 61h 65 system memory map 2 end address low 22h 62h 66 system memory map 2 end address high 23h 63h 66 card memory map 2 offset address low 24h 64h 67 card memory map 2 offset address high 25h 65h 68 ata control 26h 66h ? extension registers ? on page 70 75 scratchpad 27h 67h ?? system memory map 3 start address low 28h 68h ? memory window mapping registers ? on page 64 64 system memory map 3 start address high 29h 69h 65 system memory map 3 end address low 2ah 6ah 60 system memory map 3 end address high 2bh 6bh 66 card memory map 3 offset address low 2ch 6ch 67 card memory map 3 offset address high 2dh 6dh 68 table 11. index registers (sheet 2 of 3) register name index value chapter page number socket a socket b 1 1. socket b is available on the dual-socket pd6722. 2. this register affects both sockets (it is not specific to either socket). 3. these registers are not available on the pd6710.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 44 datasheet 6.2 data extended index: 3 scratchpad data mask 0 data mask 1 extension control 1 (formerly dma control) maximum dma acknowledge delay reserved external data extension control 2 2eh 6eh ? extension registers ? on page 70 77 extended index 00h extended index 01h extended index 02h extended index 03h extended index 04h extended index 05h ? 09h extended index 0ah ? extended index 0bh ? 77 78 78 79 ? 81 83 extended data 2fh 6fh 77 system memory map 4 start address low 30h 70h ? memory window mapping registers ? on page 64 64 system memory map 4 start address high 31h 71h 65 system memory map 4 end address low 32h 72h 66 system memory map 4 end address high 33h 73h 66 card memory map 4 offset address low 34h 74h 62 card memory map 4 offset address high 35h 75h 68 card i/o map 0 offset address low 36h 76h ? i/o window mapping registers ? on page 58 62 card i/o map 0 offset address high 37h 77h 62 card i/o map 1 offset address low 38h 78h 62 card i/o map 1 offset address high 39h 79h 62 setup timing 0 3ah 7ah ? timing registers ? on page 84 84 command timing 0 3bh 7bh 85 recovery timing 0 3ch 7ch 86 setup timing 1 3dh 7dh 84 command timing 1 3eh 7eh 85 recovery timing 1 3fh 7fh 86 register name: data index: n/a register per: chip register compatibility type 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data table 11. index registers (sheet 3 of 3) register name index value chapter page number socket a socket b 1 1. socket b is available on the dual-socket pd6722. 2. this register affects both sockets (it is not specific to either socket). 3. these registers are not available on the pd6710.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 45 the data register is accessed at 03e1h. this register indicates the contents of the register at the device/socket/register index selected by the index register.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 46 datasheet 7.0 chip control registers 7.1 chip revision bits 3:0 ? revision this field indicates compatibility with the 82365sl a-step. bits 7:6 ? interface id these bits identify what type of interface this controller supports. register name: chip revision index: 00h register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 interface id revision r:10 r:0 r:0 r:0010 1 1. value for the current stepping only. 00 i/o only. 01 memory only. 10 memory and i/o. 11 reserved.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 47 7.2 interface status bits 1:0 ? battery voltage detect these bits are used by pc card support software and firmware to indicate the amount of capacity left in the battery in battery-backed cards in memory card interface mode only. in i/o card interface mode, bit 0 indicates the state of the bvd1/-stschg pin ( table 2 ). bit 1 status should be ignored in i/o card interface mode. bits 3:2 ? card detect these bits indicate the state of the -cd1 and -cd2 pins ( table 2 ). register name: interface status index: 01h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3 bit 2bit 1bit 0 -vpp_valid rdy wp -cd2 -cd1 bvd2 bvd1 v pp valid card power on ready/busy* write protect card detect battery voltage detect r 1 r:0 r 2 r 3 r 4 r 5 1. bit 7 is the inversion of the value of the -vpp_valid pin ( ta b l e 1 ). 2. bit 5 is the value of the rdy/-ireq pin ( table 2 ). 3. bit 4 is the value of the wp/-iois16 pin ( table 2 ). 4. bits 3:2 are the inversion of the values of the -cd1 and -cd2 pins ( table 2 ). 5. bits 1:0 are the values of the bvd1/-stschg and bvd2/-spkr pins ( table 2 ). bvd2 input level bvd1 input level bit 1 bit 0 pc card interpretation low low 0 0 card data lost low high 0 1 battery low warning high low 1 0 card data lost high high 1 1 battery/data okay -cd2 level -cd1 level bit 3 bit 2 card detect status high high 0 0 either no card or card is not fully inserted high low 0 1 card is not fully inserted low high 1 0 card is not fully inserted low low 1 1 card is fully inserted
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 48 datasheet bit 4 ? write protect this bit indicates the state of the wp/-iois16 pin ( table 2 ) on the card and has meaning only in memory card interface mode. bit 5 ? ready/busy* this bit indicates the state of the rdy/-ireq pin ( table 2 ) on the card. if the card has been configured for i/o, then this bit will not be valid. bit 6 ? card power on this status bit indicates whether power to the card is on. refer to table 11 on page 42 for details. bit 7 ? v pp valid this bit indicates the status of the -vpp_valid pin ( table 1 ). 7.3 power control 0 card is not write protected. 1 card is write protected. 0 card is not ready. 1 card is ready. 0 power to the card is not on. 1 power to the card is on. 0 this status bit indicates a logic high at the -vpp_valid pin. 1 this status bit indicates a logic low at the -vpp_valid pin. register name: power control index: 02h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 card enable compatibility bit auto-power v cc power compatibility bits v pp 1 power rw:0 rw:0 rw:0 rw:0 rw:00 rw:00
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 49 table 12. enabling of socket power controls pwrgood level power control register -cd1 and -cd2 both active low interface status register (see page 47) -vcc_3 and -vcc_5 levels vpp1_pgm and vpp1_vcc levels bit 4: v cc power bit 5: auto- power bit 6: card power on low x x x 0 inactive high inactive low high 0 x x 0 inactive high inactive low high 1 0 x 1 activated per misc control 1 register, bit 1 activated per power control register, bits 1 and 0 high 1 1 no 0 inactive high inactive low high 1 1 yes 1 activated per misc control 1 register, bit 1 activated per power control register, bits 1 and 0 table 13. enabling of outputs to card socket pwrgood level -cd1 and -cd2 both active low power control register pd67xx signal outputs to socket bit 4: v cc power bit 7: card enable low x x x high impedance high no x x high impedance high yes 0 0 high impedance high yes 0 1 enabled high yes 1 0 high impedance high yes 1 1 enabled bit name value description v cc power 1 enables v cc to level described by v cc 3.3v (see ? bit 4 ? vcc power ? on page 50 ) auto-power 1 enables auto-power mode card enable 1 enables socket output drivers
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 50 datasheet bits 1:0 ? v pp 1 power these bits are intended to be used to control the power to the v pp 1 pin of the pc card. bit 4 ? v cc power depending on the value of bit 5 below, setting this bit to ? 1 ? will cause power to be applied to the card. the v cc 3.3v bit (see bit 1, ? misc control 1 ? on page 70 ) determines whether 3.3v or 5v power is applied. bit 5 ? auto-power when this bit is set to ? 1 ? , the pd67xx causes power to the card to be turned on and off automatically with the insertion and removal of a pc card from the socket. bit 7 ? card enable when this bit is ? 1 ? , the outputs to the pc card are enabled if a card is present and card power is being supplied. the pins affected include: -ce2, -ce1, -iord, -iowr, -oe, -reg, reset, a[25:0], d[15:0], and -we (see table 2 ). v pp 1 power bit 1 bit 0 vpp_pgm vpp_vcc pc card intended socket function 0 0 inactive low inactive low zero volts to pc card socket v pp 1 pin 0 1 inactive low active high 1 selected card v cc to pc card socket v pp 1 pin 1 0 active high a inactive low +12v to pc card socket v pp 1 pin 1 1 inactive low inactive low zero volts to pc card socket v pp 1 pin 1. under conditions where v pp 1 power is activated. see ? power control ? on page 48 . 0 power is not applied to the card: the -vcc_3 and -vcc_5 socket power control pins are inactive high. 1 power is applied to the card: if bit 5 is ? 0 ? , or bit 5 is ? 1 ? and -cd2 and -cd1 are active low, then the selected -vcc_3 or -vcc_5 socket power control pin is active low. 0 v cc and v pp 1 power control signals are activated independent of the socket ? s -cd2 and - cd1 input levels. 1 v cc and v pp 1 power control signals are only activated if the socket ? s -cd2 and -cd1 inputs are active low. 0 outputs to card socket are not enabled and are floating. 1 outputs to card socket are enabled if -cd1 and -cd2 are active low and bit 4 is ? 1 ? .
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 51 7.4 interrupt and general control bits 3:0 ? card irq select these bits determine which irq will occur when the card causes an interrupt through the rdy/ -ireq pin on the pc card connector. bit 4 ? enable manage int this bit determines how management interrupts will occur. register name: interrupt and general control index: 03h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 ring indicate enable card reset* card is i/o enable manage int card irq select rw:0 rw:0 rw:0 rw:0 rw:0000 0000 irq disabled 0001 reserved 0010 reserved 0011 irq 3 0100 irq 4 0101 irq 5 0110 reserved 0111 irq 7 1000 reserved 1001 irq 9 (on the pd6722, this output may alternately be used as an isa bus dack* signal) 1010 irq 10 (on the pd6722, this output may alternately be used as an isa bus drq signal) 1011 irq 11 1100 irq 12 (this output may alternately be used for led) 1101 reserved 1110 irq 14 1111 irq 15 (this output may alternately be used for ring indicate) 0 card status management interrupts occur as programmed by management irq select bits (bits 7:4 of management interrupt configuration register, see ? bits 7:4 ? management irq select ? on page 55 ). 1 card status management interrupts are redirected to the -intr line instead of the programmed irq pin.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 52 datasheet bit 5 ? card is i/o this bit determines how dual-function socket interface pins will be used. bit 6 ? card reset* this bit determines whether the reset signal (see table 2 on page 20 ) to the card is active or inactive. when the card enable bit (see ? bit 7 ? card enable ? on page 50 ) is ? 0 ? , the reset signal to the card will be high-impedance. see chapter 10 for further description of ata mode functions. bit 7 ? ring indicate enable this bit determines whether the -stschg input pin is used to activate the irq15 pin in conjunction with misc control 2 , irq15 is ri out (see ? bit 7 ? irq15 is ri out ? on page 74 ). this bit has no significance when the card socket is configured for memory card operation. 7.5 card status change this register indicates the source of a management interrupt generated by the pd67xx. note: the corresponding bit in the management interrupt configuration register must be set to ? 1 ? to enable each specific status change detection. 0 memory card interface mode: card socket configured to support memory cards. dual-function socket interface pins perform memory card-type interface functions. 1 i/o card interface mode: card socket configured to support i/o/memory card-type interface functions. dual-function socket interface pins perform i/o/memory card-type interface functions. 0 the reset signal to the card socket is set active (high for normal, low for ata mode). 1 the reset signal to the card socket is set inactive (low for normal, high for ata mode). 0 bvd1/-stschg pin is status change function. 1 bvd1/-stschg pin is ring indicate input pin from card. register name: card status change index: 04h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 card detect change ready change battery warning change battery dead or status change r:0 r:0 r:0 r:0 r:0 r:0 r:0 r:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 53 bit 0 ? battery dead or status change when the socket is configured for memory card support, this bit is set to ? 1 ? when a bvd1 battery dead high-to-low transition has been detected. when the socket is configured for i/o card support, this bit is set to ? 1 ? when the bvd1/-stschg pin (see table 2 on page 20 ) changes from either high to low or low to high. this bit is reset to ? 0 ? whenever this register is read. in i/o card interface mode, function of this bit is not affected by bit 7 of the interrupt and general control register. bit 1 ? battery warning change when a socket is configured for memory card support, this bit is set to ? 1 ? when a high-to-low transition on bvd2 occurs indicating a battery warning was detected. this bit should be ignored when the socket is configured for i/o card support. this bit is reset to ? 0 ? whenever this register is read. bit 2 ? ready change when this bit is ? 1 ? , a change has occurred in the card rdy/-ireq pin (see table 2 on page 20 ). this bit will always read 0 when the card is configured as an i/o card. this bit is reset to ? 0 ? whenever this register is read. bit 3 ? card detect change when this bit is ? 1 ? , a change has occurred on the -cd1 or -cd2 pins (see table 2 on page 20 ). this bit is reset to ? 0 ? whenever this register is read. 0 a transition (from high to low for memory card support or either high to low or low to high for i/o card support) on the bvd1/-stschg pin has not occurred since this register was last read. 1 a transition on the bvd1/-stschg pin has occurred. 0 a transition (from high to low) on the bvd2 pin has not occurred since this register was last read. 1 a transition on the bvd2 pin has occurred. 0 a transition on the rdy/-ireq pin has not occurred since this register was last read. 1 a transition on the rdy/-ireq pin has occurred. 0 a transition on the -cd1 or -cd2 pins has not occurred since this register was last read. 1 a transition on the -cd1 or -cd2 pins has occurred.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 54 datasheet 7.6 management interrupt configuration this register controls which status changes may cause management interrupts and at which pin the management interrupts will appear. bit 0 ? battery dead or status change enable when this bit is ? 1 ? , a management interrupt will occur when the card status change register ? s battery dead or status change bit (see ? bit 0 ? battery dead or status change ? on page 53 ) is ? 1 ? . this allows management interrupts to be generated on changes in level of the bvd1/ -stschg pin. bit 1 ? battery warning enable when this bit is ? 1 ? , a management interrupt will occur when the card status change register ? s battery warning change bit (see ? bit 1 ? battery warning change ? on page 53 ) is ? 1 ? . this bit is ignored when the card socket is in i/o mode. bit 2 ? ready enable when this bit is ? 1 ? , a management interrupt will occur when the card status change register ? s ready change bit (see ? bit 1 ? battery warning change ? on page 53 ) is ? 1 ? . register name; management interrupt configuration index: 05h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 management irq select card detect enable ready enable battery warning enable battery dead or status change enable rw:0000 rw:0 rw:0 rw:0 rw:0 0 battery dead or status change management interrupt disabled. 1 if battery dead or status change is ? 1 ? , a management interrupt will occur. 0 battery warning change management interrupt disabled. 1 if battery warning change is ? 1 ? , a management interrupt will occur. 0 ready change management interrupt disabled. 1 if ready change is ? 1 ? , a management interrupt will occur.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 55 bit 3 ? card detect enable when this bit is ? 1 ? , a management interrupt will occur when the card status change register ? s card detect change bit (see ? bit 3 ? card detect change ? on page 53 ) is ? 1 ? . bits 7:4 ? management irq select these bits determine which interrupt pin will be used for card status change management interrupts. 7.7 mapping enable 0 card detect change management interrupt disabled. 1 if card detect change is ? 1 ? , a management interrupt will occur. 0000 irq disabled 0001 reserved 0010 reserved 0011 irq 3 0100 irq 4 0101 irq 5 0110 reserved 0111 irq 7 1000 reserved 1001 irq 9 (on the pd6722, this output may alternately be used as an isa bus dack* signal) 1010 irq 10 (on the pd6722, this output may alternately be used as an isa bus drq signal) 1011 irq 11 1100 irq 12 (this output may alternately be used for led) 1101 reserved 1110 irq 14 1111 irq 15 (this output may alternately be used for ring indicate) register name: mapping enable index: 06h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o map 1 enable i/o map 0 enable memcs16 full decode memory map 4 enable memory map 3 enable memory map 2 enable memory map 1 enable memory map 0 enable rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 56 datasheet bit 0 ? memory map 0 enable when this bit is ? 1 ? , the memory mapping registers for memory space 0 will be enabled and the controller will respond to memory accesses in the memory space defined by those registers. bit 1 ? memory map 1 enable when this bit is ? 1 ? , the memory mapping registers for memory space 1 will be enabled and the controller will respond to memory accesses in the memory space defined by those registers. bit 2 ? memory map 2 enable when this bit is ? 1 ? , the memory mapping registers for memory space 2 will be enabled and the controller will respond to memory accesses in the memory space defined by those registers. bit 3 ? memory map 3 enable when this bit is ? 1 ? , the memory mapping registers for memory space 3 will be enabled and the controller will respond to memory accesses in the memory space defined by those registers. bit 4 ? memory map 4 enable when this bit is ? 1 ? , the memory mapping registers for memory space 4 will be enabled and the controller will respond to memory accesses in the memory space defined by those registers. bit 5 ? memcs16 full decode this bit is not used. all addresses are used to determine the level of memcs16*. 0 memory mapping registers for memory space 0 disabled. 1 memory mapping registers for memory space 0 enabled. 0 memory mapping registers for memory space 1 disabled. 1 memory mapping registers for memory space 1 enabled. 0 memory mapping registers for memory space 2 disabled. 1 memory mapping registers for memory space 2 enabled. 0 memory mapping registers for memory space 3 disabled. 1 memory mapping registers for memory space 3 enabled. 0 memory mapping registers for memory space 4 disabled. 1 memory mapping registers for memory space 4 enabled.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 57 bit 6 ? i/o map 0 enable when this bit is ? 1 ? , the i/o mapping registers for i/o space 0 will be enabled and the controller will respond to i/o accesses in the i/o space defined by those registers. bit 7 ? i/o map 1 enable when this bit is ? 1 ? , the i/o mapping registers for i/o space 1 will be enabled and the controller will respond to i/o accesses in the i/o space defined by those registers. 0 i/o mapping registers for i/o space 0 disabled. 1 i/o mapping registers for i/o space 0 enabled. 0 i/o mapping registers for i/o space 1 disabled. 1 i/o mapping registers for i/o space 1 enabled.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 58 datasheet 8.0 i/o window mapping registers the i/o windows must never include 3e0h and 3e1h. 8.1 i/o window control bit 0 ? i/o window 0 size when bit 1 below is ? 0 ? , this bit determines the size of the data path to i/o window 0. when bit 1 is ? 1 ? , this bit is ignored. bit 1 ? auto-size i/o window 0 this bit determines the data path to i/o window 0. note that when this bit is ? 1 ? , the -iois16 signal (see table 2 on page 20 ) determines the width of the data path to the card. bit 3 ? timing register select 0 this bit determines the access timing specification for i/o window 0 (see ? setup timing 0 ? 1 ? on page 84 ). register name: i/o window control index: 07h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 timing register select 1 compatibility bit auto-size i/o window 1 i/o window 1 size timing register select 0 compatibility bit auto-size i/o window 0 i/o window 0 size rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 0 8-bit data path to i/o window 0. 1 16-bit data path to i/o window 0. 0 i/o window 0 size (see bit 0 above) determines the data path to i/o window 0. 1 the data path to i/o window 0 will be determined based on -iois16 returned by the card. 0 accesses made with timing specified in timing set 0. 1 accesses made with timing specified in timing set 1.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 59 bit 4 ? i/o window 1 size when bit 5 below is ? 0 ? , this bit determines the size of the data path to i/o window 1. when bit 5 is ? 1 ? , this bit is ignored. bit 5 ? auto-size i/o window 1 this bit determines the width of the data path to i/o window 1. note that when this bit is ? 1 ? , the -iois16 signal (see table 2 on page 20 ) determines the window size. this bit must be set for proper ata mode operation (see ? ata mode operation ? on page 88 ). bit 7 ? timing register select 1 this bit determines the access timing specification for i/o window 1 (see ? setup timing 0 ? 1 ? on page 84 ). 8.2 system i/o map 0 ? 1 start address low there are two separate system i/o map start address low registers, each with identical fields. these registers are located at the following indexes: index system i/o map start address low 8h system i/o map 0 start address low ch system i/o map 1 start address low 0 8-bit data path to i/o window 1. 1 16-bit data path to i/o window 1. 0 i/o window 1 size (see bit 4) determines the data path to i/o window 1. 1 the data path to i/o window 1 will be determined based on -iois16 returned by the card. 0 accesses made with timing specified in timing set 0. 1 accesses made with timing specified in timing set 1. register name: system i/o map 0 ? 1 start address low index: 08h, 0ch register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 start address 7:0 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 60 datasheet bits 7:0 ? start address 7:0 this register contains the least-significant byte of the address that specifies the beginning of the i/o space within the corresponding i/o map. i/o accesses that are equal or above this address and equal or below the corresponding system i/o map end address will be mapped into the i/o space of the corresponding pc card. the most-significant byte is located in the system i/o map 0 ? 1 start address high register (see ? system i/o map 0 ? 1 start address high ? on page 60 ). 8.3 system i/o map 0 ? 1 start address high there are two separate system i/o map start address high registers, each with identical fields. these registers are located at the following indexes: index system i/o map start address high 9h system i/o map 0 start address high dh system i/o map 1 start address high bits 15:8 ? start address 15:8 this register contains the most-significant byte of the start address. see the description of the start address field associated with bits 7:0 of the system i/o map 0 ? 1 start address low register. 8.4 system i/o map 0 ? 1 end address low there are two separate system i/o map end address low registers, each with identical fields. these registers are located at the following indexes: register name: system i/o map 0 ? 1 start address high index: 09h, 0dh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 start address 15:8 rw:00000000 register name: system i/o map 0 ? 1 end address low index: 0ah, 0eh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 end address 7:0 rw:00000000
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 61 index system i/o map end address low ah system i/o map 0 end address low eh system i/o map 1 end address low bits 7:0 ? end address 7:0 this register contains the least-significant byte of the address that specifies the termination of the i/ o space within the corresponding i/o map. i/o accesses that are equal or below this address and equal or above the corresponding system i/o map start address will be mapped into the i/o space of the corresponding pc card. the most-significant byte is located in the system i/o map 0 ? 1 end address high register (see ? system i/o map 0 ? 1 end address high ? on page 61 ). 8.5 system i/o map 0 ? 1 end address high there are two separate system i/o map end address high registers, each with identical fields. these registers are located at the following indexes: index system i/o map end address high bh system i/o map 0 end address high fh system i/o map 1 end address high bits 15:8 ? end address 15:8 this register contains the most-significant byte of the end address. see the description of the end address field associated with bits 7:0 of the system i/o map 0 ? 1 end address low register (see ? system i/o map 0 ? 1 end address low ? on page 60 ). register name: system i/o map 0 ? 1 end address high index: 0bh, 0fh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 15:8 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 62 datasheet 8.6 card i/o map 0 ? 1 offset address low there are two separate card i/o map offset address low registers, each with identical fields. these registers are located at the following indexes: index card i/o map offset address low 36h card i/o map 0 offset address low 38h card i/o map 1 offset address low bits 7:1 ? offset address 7:1 this register contains the least-significant byte of the quantity that will be added to the host i/o address; this will determine the pc card i/o map location where the i/o access will occur. the most-significant byte is located in the card i/o map 0 ? 1 offset address high register (see ? card i/o map 0 ? 1 offset address high ? on page 62 ). 8.7 card i/o map 0 ? 1 offset address high there are two separate card i/o map offset address high registers, each with identical fields. these registers are located at the following indexes: index card i/o map offset address high 37h card i/o map 0 offset address high 39h card i/o map 1 offset address high register name: card i/o map 0 ? 1 offset address low index: 36h, 38h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 offset address 7:1 0 1 rw:0000000 rw:0 1. this bit must be programmed to ? 0 ? . register name: card i/o map 0 ? 1 offset address high index: 37h, 39h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 offset address 15:8 rw:00000000
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 63 bits 15:8 ? offset address 15:8 this register contains the most-significant byte of the offset address. see the description of the end address field associated with bits 7:1 of the card i/o map 0 ? 1 offset address low register (see ? card i/o map 0 ? 1 offset address low ? on page 62 ).
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 64 datasheet 9.0 memory window mapping registers the following information about the memory map windows is important: the memory window mapping registers determine where in the isa memory space and pc card memory space accesses will occur. there are five memory windows that can be used independently. the memory windows are enabled and disabled using the mapping enable register (see ? mapping enable ? on page 55 ). to specify where in the isa space a memory window is mapped, start and end addresses are specified. a memory window is selected whenever the appropriate memory map enable bit (see ? mapping enable ? ) is set, and when the isa address is greater than or equal to the appropriate system memory map start address register (see ? system memory map 0 ? 4 start address low ? on page 64 ) and the isa address is less than or equal to the appropriate system memory map end address register (see ? system memory map 0 ? 4 end address low ? on page 66 ). start and end addresses are specified with isa address bits 23:12. this sets the minimum size of a memory window to 4k bytes. memory windows are specified in the isa address from 64 kbytes to 16 mbytes (0010000h ? ffffffh). note that no memory window can be mapped in the first 64 kbytes of the isa address space. to ensure proper operation, none of the windows can overlap in the isa address space. 9.1 system memory map 0 ? 4 start address low there are five separate system memory map start address low registers, each with identical fields. these registers are located at the following indexes: index system memory map start address low 10h system memory map 0 start address low 18h system memory map 1 start address low 20h system memory map 2 start address low 28h system memory map 3 start address low 30h system memory map 4 start address low register name: system memory map 0 ? 4 start address low index: 10h, 18h, 20h, 28h, 30h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 start address 19:12 rw:00000000
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 65 bits 7:0 ? start address 19:12 this register contains the least-significant byte of the address that specifies where in the memory space the corresponding memory map will begin. memory accesses that are equal or above this address and equal or below the corresponding system memory map end address will be mapped into the memory space of the corresponding pc card. the most-significant four bits are located in the system memory map 0 ? 4 start address high register (see ? system memory map 0 ? 4 start address high ? on page 65 ). 9.2 system memory map 0 ? 4 start address high there are five separate system memory map start address high registers, each with identical fields. these registers are located at the following indexes: index system memory map start address high 11h system memory map 0 start address high 19h system memory map 1 start address high 21h system memory map 2 start address high 29h system memory map 3 start address high 31h system memory map 4 start address high bits 3:0 ? start address 23:20 this field contains the most-significant four bits of the start address. see the description of the start address field associated with bits 7:0 of the system memory map 0 ? 4 start address low register (see ? system memory map 0 ? 4 start address low ? on page 64 ). bit 7 ? window data size this bit determines the data path size to the card. register name: system memory map 0 ? 4 start address high index: 11h, 19h, 21h, 29h, 31h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 window data size compatibility bit scratchpad bits start address 23:20 rw:0 rw:0 rw:00 rw:0000 0 8-bit data path to the card. 1 16-bit data path to the card.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 66 datasheet 9.3 system memory map 0 ? 4 end address low there are five separate system memory map end address low registers, each with identical fields. these registers are located at the following indexes: index system memory map end address low 12h system memory map 0 end address low 1ah system memory map 1 end address low 22h system memory map 2 end address low 2ah system memory map 3 end address low 32h system memory map 4 end address low bits 7:0 ? end address 19:12 this register contains the least-significant byte of the address that specifies where in the memory space the corresponding memory map will end. memory accesses that are equal or below this address and equal or above the corresponding system memory map start address will be mapped into the memory space of the corresponding pc card. the most-significant four bits are located in the system memory map 0 ? 4 end address high register (see ? system memory map 0 ? 4 end address high ? on page 66 ). 9.4 system memory map 0 ? 4 end address high there are five separate system memory map end address high registers, each with identical fields. these registers are located at the following indexes: index system memory map end address high 13h system memory map 0 end address high 1bh system memory map 1 end address high register name: system memory map 0 ? 4 end address low index: 12h, 1ah, 22h, 2ah, 32h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 19:12 rw:00000000 register name: system memory map 0 ? 4 end address high index: 13h, 1bh, 23h, 2bh, 33h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 card timer select scratchpad bits end address 23:20 rw:00 rw:00 rw:0000
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 67 23h system memory map 2 end address high 2bh system memory map 3 end address high 33h system memory map 4 end address high 9.4.0.1 bits 3:0 ? end address 23:20 this field contains the most-significant four bits of the end address. see the description of the end address field associated with bits 7:0 of the system memory map 0 ? 4 end address low register (see ? system memory map 0 ? 4 end address low ? on page 66 ). bits 7:6 ? card timer select this field selects the timeset registers used to control socket timing for card accesses in this window address range. timeset 0 and 1 reset to values compatible with pc card standards. the mapping of bits 7:6 to timeset 0 and 1, as shown in the preceding table, is done for software compatibility with older isa bus-based pc card controllers that use isa bus wait states instead of timeset registers (see ? setup timing 0 ? 1 ? on page 84 ). 9.5 card memory map 0 ? 4 offset address low there are five separate card memory map offset address low registers, each with identical fields. these registers are located at the following indexes: i ndex card memory map offset address low 14h card memory map 0 offset address low 1ch card memory map 1 offset address low 24h card memory map 2 offset address low 2ch card memory map 3 offset address low 34h card memory map 4 offset address low 00 selects timer set 0. 01 selects timer set 1. 10 selects timer set 1. 11 selects timer set 1. register name: card memory map 0 ? 4 offset address low index: 14h, 1ch, 24h, 2ch, 34h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 19:12 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 68 datasheet bits 7:0 ? offset address 19:12 this register contains the least-significant byte of the quantity that will be added to the host memory address, which will determine where the memory access will occur in the pc card memory map. the most-significant six bits are located in the card memory map 0 ? 4 offset address high register (see ? card memory map 0 ? 4 offset address high ? on page 68 ). 9.6 card memory map 0 ? 4 offset address high there are five separate card memory map offset address high registers, each with identical fields. these registers are located at the following indexes: index card memory map offset address high 15h card memory map 0 offset address high 1dh card memory map 1 offset address high 25h card memory map 2 offset address high 2dh card memory map 3 offset address high 35h card memory map 4 offset address high bits 5:0 ? offset address 25:20 this field contains the most-significant six bits of the offset address. see the description of the offset address field associated with bits 7:0 of the card memory map 0 ? 4 offset address low register (see ? card memory map 0 ? 4 offset address low ? on page 67 ). bit 6 ? reg setting this bit determines whether -reg ( table 2 ) will be active for accesses made through this window. card information structure (cis) memory is accessed by setting this bit to ? 1 ? . register name: card memory map 0 ? 4 offset address high index: 15h, 1dh, 25h, 2dh, 35h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write protect reg setting offset address 25:20 rw:0 rw:0 rw:000000 0 -reg (see table 2 on page 20 ) is not active for accesses made through this window. 1 -reg is active for accesses made through this window.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 69 bit 7 ? write protect this bit determines whether writes to the card through this window are allowed. this bit only applies to memory card interface mode. note: this bit must be set to ? 0 ? and a memory card ? s ? wp ? switch must be turned off to allow writes to a card using a memory interface, such as an sram card. 0 writes to the card through this window are allowed. 1 writes to the card through this window are inhibited.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 70 datasheet 10.0 extension registers 10.1 misc control 1 bit 0 ? 5 v detect (pd6710 only) this bit is connected to pins vs1 and vs2. cards that will only operate at 3.3 v will drive this bit to ? 0 ? . bit 1 ? v cc 3.3v this bit determines which output pin is to be used to enable v cc power to the socket when card power is to be applied; it is used in conjunction with bits 5:4 of the power control register (see ? power control ? on page 48 ). bit 2 ? pulse management interrupt this bit selects level or pulse mode operation of the irq[xx] or -intr pin being used for card status change management interrupts (see table 1 ). note that a clock must be present on the incoming clk for pulsed interrupts to work. register name: misc control 1 index: 16h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 inpack enable scratchpad bits speaker enable pulse system irq pulse management interrupt v cc 3.3v 5 v detect (pd6710) reserved 1 (pd6722 ) rw:0 rw:00 rw:0 rw:0 rw:0 rw:0 r:x w:0 1. on some versions of the pd6722, this bit can be used to read levels of the a_gpstb and b_gpstb pins. 0 3.3 v card detected. 1 old or 5 v card detected. 0 -vcc_5 activated when card power is to be applied. 1 -vcc_3 activated when card power is to be applied. 0 card status change management interrupts are passed to the appropriate irq[xx] or -intr pin as level-sensitive. 1 when a card status change management interrupt occurs, the appropriate irq[xx] or -intr pin is driven with the pulse train shown in figure 11 and allows for interrupt sharing.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 71 bit 3 ? pulse system irq this bit selects level or pulse mode operation of the irq[xx] pins for interrupts from a pc card rdy/-ireq pin ( table 2 ). bit 4 ? speaker enable this bit determines whether the card -spkr pin will drive spkr_out* ( table 1 ). bit 7 ? inpack enable this bit is used to determine when to drive data onto the isa bus. figure 11. pulse mode interrupts -intr or high-z high-z irq[xx] driven low driven high 0 rdy/-ireq generated interrupts are passed to the irq[xx] pin as level-sensitive. 1 when a rdy/-ireq interrupt occurs, the irq[xx] pin is driven with the pulse train shown in figure 11 and allows for interrupt sharing. 0 spkr_out* is high-impedance. 1 spkr_out* is driven from the xor of -spkr from each enabled socket. 0 -inpack pin ( table 2 ) ignored. 1 -inpack pin used to control data bus drivers during i/o read from the socket.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 72 datasheet 10.2 fifo control bit 7 ? empty write fifo this bit controls fifo operation and reports fifo status. when this bit is written to ? 1 ? , all data in the fifo is lost. during read operations when this bit is ? 1 ? , the fifo is empty. during read operations when this bit is ? 0 ? , data is still in the fifo. this bit is used to ensure the fifo is empty before changing timing registers. fifo contents will be lost whenever any of the following occur: pwrgood pin ( table 1 ) is ? 0 ? . the card is removed. v cc power bit (see ? bit 4 ? vcc power ? on page 50 ) is programmed to ? 0 ? . 10.3 misc control 2 register name: fifo control index: 17h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 empty write fifo scratchpad bits a a. rw rw:0000000 1. because a write will flush the fifo, these scratchpad bits should be used only when card activity is guaranteed not to occur. value i/o read i/o write 0 fifo not empty no operation occurs; default on reset 1 fifo empty flush the fifo register name: misc control 2 index: 1eh register per: chip register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 irq15 is ri out dma system (pd6722) three-state bit 7 drive led enable 5v core suspend low-power dynamic mode bypass frequency synthesizer rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:1 rw:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 73 bit 0 ? bypass frequency synthesizer this bit determines internal time base. bit 1 ? low-power dynamic mode this bit determines whether low-power dynamic mode is enabled. for maximum operational power savings, keep this bit set to ? 1 ? . bit 2 ? suspend this bit enables suspend mode. after entering suspend, aen should be pulled high for lowest power consumption. when this bit is high and aen is high, all isa bus interface inputs are turned off. in 82386sl systems when the processor is in suspend mode, the isa bus interface signals float; this feature will prevent high current flow in the pd67xx inputs. bit 3 ? 5v core this bit selects input threshold circuits for use when 3.3 or 5.0 volts is connected to the pd67xx core_vdd pins. this bit must be set to ? 0 ? when the core_vdd pins are connected to 3.3 volts to preserve ttl-compatible input thresholds to the card socket. bit 4 ? drive led enable note: this bit should be set to ? 0 ? if in memory card interface mode. this bit determines whether -spkr is used to drive an led on the irq12 ( table 1 ) for disk drives. 0 normal operation, internal clock = clk input frequency x 7/4. 1 internal clock = clk input frequency (see table 1 ). 0 clock runs always. 1 normal operation, stop clock when possible. 0 normal operation. 1 stop frequency synthesizer, enable all low-power modes and disable socket access. 0 normal operation: use when core_vdd pin is connected to 3.3 volts. 1 selects input thresholds for use when 5.0 volts is connected to the pd67xx core_vdd pins. 0 irq12 operates normally. 1 irq12 becomes an open-drain output suitable for driving an led (driven whenever the card - spkr output is turned on, and the corresponding speaker is led input bit (see ? bit 1 ? speaker is led input ? on page 76 ) is set).
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 74 datasheet bit 5 ? three-state bit 7 this bit enables floppy change bit compatibility. bit 6 ? dma system (pd6722 only) on the pd6710, this bit is reserved. on the pd6722, this bit is used to configure system interface signals for normal or dma operation. at reset, the signals irq9, irq10, and -vpp_valid are in non-dma mode, and this bit is set to ? 0 ? . when this bit is set to ? 1 ? , the irq9, irq10, and -vpp_valid pins are reconfigured for system bus dma interfacing. refer to ? dma operation (pd6722 only) ? on page 97 for a functional description of these pins during dma operation. bit 7 ? irq15 is ri out this bit determines the function of the irq15 pin. when configured for ring indicate, irq15 is used to resume a processor with nmi or smi such as an 82486sl when a high-to-low change is detected on the -stschg pin. 10.4 chip information 0 normal operation. 1 for socket i/o at address 03f7h and 0377h, do not drive bit 7. 0 configured for non-dma mode on the pd6722. 1 configured for dma mode on the pd6722. 0 normal irq15 operation. 1 irq15 is connected to ring indicate pin on the host processor. register name: chip information index: 1fh register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc card controller identifi- cation dual/single socket* pd67xx revision level reserved r:11 r:n 1 r:nnnn 2 r:n 3 1. the value for pd6710 is ? 0 ? , and the value for pd6722 is ? 1 ? . 2. this read-only value depends on the revision level of the pd67xx chip. 3. the value for pd6722 is ? 1 ? . the value for the pd6710 is ? 0 ? .
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 75 bits 4:1 ? pd67xx revision level this field identifies the revision of the controller. the initial value is ? 111 ? . bit 5 ? dual/single socket* this bit specifies the number of sockets supported by the pd67xx. bits 7:6 ? pc card controller identification this field identifies a pc card controller device. after chip reset or doing an i/o write to this register, the first read of this register will return ? 11 ? . on the next read, this field will be ? 00 ? . this pattern of toggling data on subsequent reads can be used by software to determine presence of a pc card controller in a system or to determine occurrence of a device reset. 10.5 ata control bit 0 ? ata mode this bit reconfigures the particular socket as an ata drive interface. refer to table 17 on page 88 for pc card socket pin definitions in ata mode. 0 chip identified as a single-socket controller. 1 chip identified as a dual-socket controller. 00 second read after i/o write to this register. 11 first read after i/o write to this register. register name: ata control index: 26h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a25/csel a24/m/s* a23/vu a22 a21 scratchpad bit speaker is led input ata mode rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 0 normal operation. 1 configures the socket interface to handle ata-type disk drives.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 76 datasheet bit 1 ? speaker is led input this bit changes the function of the bvd2/-spkr/-led pin (see table 2 on page 20 ) from digital speaker input to disk status led input. when in i/o card interface mode or ata mode, setting this bit to ? 1 ? reconfigures the bvd2/-spkr/-led input pin to serve as a -led input from the socket. note: this bit should be set to ? 0 ? if in memory card interface mode. bit 3 ? a21 in ata mode, the value in this bit is applied to the ata a21 pin and is vendor-specific. certain ata drive vendor-specific performance enhancements beyond the pc card standard may be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 4 ? a22 in ata mode, the value in this bit is applied to the ata a22 pin and is vendor-specific. certain ata drive vendor-specific performance enhancements beyond the pc card standard may be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 5 ? a23/vu in ata mode, the value in this bit is applied to the ata a23 pin and is vendor-specific. certain ata drive vendor-specific performance enhancements beyond the pc card standard may be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 6 ? a24/m/s* in ata mode, the value in this bit is applied to the ata a24 pin and is vendor-specific. certain ata drive vendor-specific performance enhancements beyond the pc card standard may be controlled through use of this bit. this bit has no hardware control function when not in ata mode. bit 7 ? a25/csel in ata mode, the value in this bit is applied to the ata a25 pin and is vendor-specific. certain ata drive vendor-specific performance enhancements beyond the pc card standard may be controlled through use of this bit. this bit has no hardware control function when not in ata mode. 0 normal operation. 1 the pc card -spkr pin will be used to drive irq12 if drive led enable (see ? bit 4 ? drive led enable ? on page 73 ) is set.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 77 10.6 extended index in the pd6722 only, this register controls which of the following registers at index 2fh can be accessed: 10.7 extended data the data in this register allows the registers indicated by the extended index register to be read and written. the value of this register is the value of the register selected by the extended index register. register name: extended index index: 2eh register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 extended index rw:00000000 register name at index 2fh extended register index scratchpad 00h data mask 0 01h data mask 1 02h extension control 1 (formerly named dma control) 03h maximum dma acknowledge delay 04h reserved 05h ? 09h external data 0ah extension control 2 0bh register name: extended data index: 2fh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extended data
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 78 datasheet 10.7.1 data mask 0 ? 1 data mask 0 is the mask register for i/o map 0. for each bit set in the data mask select 0 field, the corresponding data bit will not be driven when the host addresses pc card i/o addresses in the i/o map 0 range. if this register is set to 00h, then all data bits will be driven from the pc card to the isa bus (this is the reset condition). if any bits are set to ? 1 ? , accesses to the i/o map 0 range of i/o on the pc card will be forced to 8-bit operation on the isa side. if, for example, i/o map 0 registers are set for the range 3f7h to 3f7h, i/o map 1 registers are set for the range 3f0h to 3f6h, data mask select 0 is set to 7fh, and a floppy drive is the pc card device, then the conflict between the floppy address 3f7h and the hard disk register at 3f7h would not cause a conflict on the isa bus ? the floppy change bit would be correctly presented to the host. the data mask 1 register operates the same as the data mask 0 register but acts on i/o addresses in the range indicated by the i/o map 1 registers. 10.7.2 extension control 1 (pd6722 only, formerly dma control) bit 0 ? v cc power lock this bit can be used to prevent card drivers from overriding the socket services ? task of controlling power to the card, thus preventing situations where cards are powered incorrectly. bit 1 ? auto power clear disable register name: data mask 0 ? 1 index: 2fh extended index: 01h, 02h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 data mask select 0 ? 1 rw:00000000 register name: extension control 1 index: 2fh extended index: 03h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 dma enable (pd6722) pull-up control reserved led activity enable auto power clear disable v cc power lock rw:00 rw:0 rw:00 rw:0 rw:0 rw:0 0the v cc power bit (bit 4 of power control register) is not locked. 1the v cc power bit (bit 4 of power control register) cannot be changed by software. 0 the v cc power bit (bit 4 of power control register) is reset to ? 0 ? when the card is removed. 1 the v cc power bit (bit 4 of power control register) is not affected by card removal.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 79 bit 2 ? led activity enable this bit allows the led_out* pin to reflect any activity in the card. whenever pc card cycles are in process to or from a card in either socket, led_out* will be active (low). bit 5 ? pull-up control this bit turns off the pull-ups on cd2, cd1, and a_gpstb and b_gpstb (pd6722). turning off these pull-ups can be used in addition to suspend mode to even further reduce power when cards are inserted but no card accessibility is required. even though power may or may not still be applied, all pull-ups and their associated inputs will be disabled. bit 7:6 ? dma enable (pd6722 only) on the pd6722, dma enable bits 6 and 7 enable the dma operation of the pc card socket. at reset these bits are set to ? 0 ? , and this is non-dma mode. if either or both of these bits is set, the socket is in dma mode. the three codes that cause dma mode also select the use of one of three pins for the active-low -dreq input at the pc card interface. for cards requiring dma services but also needing input acknowledge functionality, or needing to indicate the size of i/o registers within a window, or needing digital speaker or led operation, the selection of the -dreq signal to the socket is made to be as flexible as possible. 10.7.3 maximum dma acknowledge delay (pd6722 only) 0 led activity disabled. 1 led activity enabled. 0 pull-ups on cd2, cd1, a_gpstb, and b_gpstb (pd6722) are in use. 1 pull-ups on cd2, cd1, a_gpstb, and b_gpstb (pd6722) are turned off. bit 7 bit 6 pin used 01-inpack 1 0 wp/-iois16 1 1 bvd2/-spkr register name: maximum dma acknowledge delay index: 2fh extended index: 04h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 maximum dma acknowledge delay rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 80 datasheet during a dma data transfer process, an isa-based system typically follows its issuance of a dma acknowledge with a dma read or write cycle. however, during a dma write-verify operation, a system can issue a dma acknowledge without following it with a dma read or write cycle. because a dma-capable pc card receives dma acknowledgment only by reception of a dma read or write cycle, conditions may occur where the card never receives a dma acknowledge. to prevent this from happening in an isa-based system, a maximum dma acknowledge delay feature has been added that generates a ? dummy ? dma write cycle (reads dma data from the card) if there are no system-generated dma read or write cycles to the card within a programmable time. once a dma acknowledge is received from the system, the pd6722 starts counting the time from the assertion of the dack* signal until the system issues a dma read or write command (ior* or iow*). if this interval exceeds the programmed time, the pd6722 assumes that a system write- verify is in progress and generates a dummy dma write cycle at the pc card interface. this allows the passing of the dma acknowledge (and terminal count status) to the card so it can perform any intended verify-cycle functions. the maximum dma acknowledge delay (t2 as shown in figure 12 ) should be programmed to a time greater than the maximum time required from the system ? s issuance of a dma acknowledge to its issuance of a dma read or write cycle (t1 as shown in figure 12 ). the t1 time is indicated in the specifications for the systems dma cycle timing. typical system specifications for t1 are 190 ? 270 ns, making a value of 80h for the maximum dma acknowledge delay register suitable for many applications. if the pd6722 is used in an add-in card application, a value of 20h may be suitable. table 14 shows maximum dma acknowledge delay register values to be programmed for a desired maximum dma acknowledge delay. figure 12. selection of acknowledge time-out interval dreq dack* aen ior*/iow* t2 t1 t1 = time delay from dma acknowledge to ior* or iow* command (specified by system design). t2 = time to program into the maximum dma acknowledge delay register for when ior* or iow* falling edge does not occur (t2 > t1 ). table 14. maximum dma acknowledge delay register values (sheet 1 of 2) register value maximum dma acknowledge delay (25-mhz internal clock and default setup timing) 80h 7 clocks = 280 ns 40h 8 clocks = 320 ns c0h 9 clocks = 360 ns 20h 10 clocks = 400 ns a0h 11 clocks = 440 ns 60h 12 clocks = 480 ns
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 81 10.7.4 external data (pd6722 only, socket a, index 2fh) bits 7:0 ? external data this register is updated and accessed according to the setting of bits 3 and 4 of the socket a extension control 2 register (index 2fh, extended index 0bh). note: for software compatibility of external data access accross the pc card (pcmcia) controller product line, the socket a external data register should only be used as a write port and not as a read port. also for compatibility, only the lower nibble of external data should be accessed and the upper nibble should be ignored. refer to ? using gpstb pins for external port control (pd6722 only) ? on page 91 for more information on the use of the external data register. e0h 13 clocks = 520 ns 10h 14 clocks = 560 ns 90h 15 clocks = 600 ns 50h 16 clocks = 640 ns d0h 17 clocks = 680 ns 30h 18 clocks = 720 ns b0h 19 clocks = 760 ns register name: external data index: 2fh only extended index: 0ah register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 external data 7 external data 6 external data 5 external data 4 external data 3 external data 2 external data 1 external data 0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 table 14. maximum dma acknowledge delay register values (sheet 2 of 2) register value maximum dma acknowledge delay (25-mhz internal clock and default setup timing) table 15. functions of socket a external data register socket a extension control 2 function of socket a external data register bit 4: gpstb on iow* bit 3: gpstb on ior* 0 0 scratchpad 01 external read port: a_gpstb is a read buffer enable for external data on sd[15:8] 10 external write port: a_gpstb is a write latch enable for sd[15:8] to get latched to an external register. reads of socket a external data register produce the value written to the latch. 11reserved
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 82 datasheet 10.7.5 external data (pd6722 only, socket a, index 6fh) bits 7:0 ? external data this register is updated and accessed according to the setting of bits 3 and 4 of the socket b extension control 2 register (index 6fh, extended index 0bh). note: for software compatibility of external data access accross the pc card (pcmcia) controller product line, the socket b external data register should only be used as a read port and not as a write port. also for compatibility, only the lower nibble of external data should be accessed and the upper nibble should be ignored. for software compatibility with vs1# and vs2# detection software, when socket b is used as a read port, socket vs1# and vs2# signals should be connected to the external read buffer as shown in figure 15 on page 96 . refer to ? using gpstb pins for external port control (pd6722 only) ? on page 91 for more information on the use of the external data register, and ? vs1# and vs2# voltage detection ? on page 95 for more information on vs1# and vs2# detection. register name: external data index: 6fh only extended index: 0ah register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 external data 7 external data 6 external data 5 external data 4 external data 3 or b_vs2# input external data 2 or b_vs1# input external data 1 or a_vs2# input external data 0 or a_vs1# input rw:0 rw:0 rw:0 rw:0 r:0 r:0 r:0 r:0 table 16. functions of socket b external data register (pd6722 only) socket b extension control 2 function of socket b external data register bit 4: gpstb on iow* bit 3: gpstb on ior* 00 bits 7:4 ? scratchpad bits 3:2 ? socket b vs2# and vs1# levels (pd6722 only) bits 1:0 ? socket a vs2# and vs1# levels 01 external read port: b_gpstb is a read buffer enable for external data on sd[15:8]. 10 external write port: b_gpstb is a write latch enable for sd[15:8] to get latched to an external register. reads of socket b external data register produce the value written to the latch. 11reserved
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 83 10.7.6 extension control 2 (pd6722 only) bit 5 ? active-high gpstb bit 4 ? gpstb on iow* (pd6722 only) note that setting this bit forces the pull-ups on a_gpstb (pd6722) to be off, independent of the setting of the pull-up control bit (index 2fh, extended index 03h, bit 5). see ? external data (pd6722 only, socket a, index 6fh) ? on page 82 , ? using gpstb pins for external port control (pd6722 only) ? on page 91 , and ? vs1# and vs2# voltage detection ? on page 95 . bit 3 ? gpstb on ior* (pd6722 only) note that setting this bit forces the pull-ups on b_gpstb (pd6722) to be off, independent of the setting of the pull-up control bit (index 6fh, extended index 03h, bit 5). see ? external data (pd6722 only, socket a, index 6fh) ? , ? using gpstb pins for external port control (pd6722 only) ? , and ? vs1# and vs2# voltage detection ? . bit 2 ? totem-pole gpstb when gpstb outputs are totem-pole, their ? high ? level is driven to the level of the +5v pin, instead of high-impedance. register name: extension control 2 index: 2fh extended index: 0bh register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reserved active-high gpstb gpstb on iow* gpstb on ior* totem-pole gpstb reserved rw:00 rw:0 rw:0 rw:0 rw:0 rw:00 0 gpstb ouputs are active-low. 1 gpstb ouputs are active-high. 0 a_gpstb (pd6722) pins are used as voltage sense. 1 a_gpstb (pd6722) pins are used to strobe i/o writes on sd[15:8]. 0 b_gpstb (pd6722) pins (socket b) are used as voltage sense. 1 b_gpstb (pd6722) pins are used to strobe i/o reads on sd[15:8]. 0 gpstb ouputs are open-collector. 1 gpstb ouputs are totem-pole.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 84 datasheet 11.0 timing registers the following information about the timing registers is important: all timing registers take effect immediately and should only be changed when the fifo is empty (see the fifo control register on ? fifo control ? on page 72 ). selection of timing 0 or timing 1 register sets is controlled by i/o window control , bit 3 and/or bit 7 (see ? i/o window control ? on page 58 ). 11.1 setup timing 0 ? 1 there are two separate setup timing registers, each with identical fields. these registers are located at the following indexes: i ndex setup timing 3ah setup timing 0 3dh setup timing 1 the setup timing register for each timing set controls how long a pc card cycle ? s command (that is, -oe, -we, -iord, -iowr; see table 2 on page 20 ) setup will be, in terms of the number of internal clock cycles. the overall command setup number of clocks s is programmed by selecting a 2-bit prescaling value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command setup timing length according to the following formula: s = ( n pres n val ) + 1 the value of s , representing the number of internal clock cycles for command setup, is then multiplied by the internal clock ? s period to determine the command setup time (see ? pc card bus timing calculations ? on page 109 for further discussion). bits 5:0 ? setup multiplier value this field indicates an integer value n val from 0 to 63; it is combined with a prescalar value (bits 7:6) to control the length of setup time before a command becomes active. register name: setup timing 0 ? 1 index: 3ah, 3dh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 setup prescalar select setup multiplier value rw:00 rw:000001
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 85 bits 7:6 ? setup prescalar select this field chooses one of four prescalar values n pres that are combined with the value of the setup multiplier value (bits 5:0) to control the length of setup time before a command becomes active. 11.2 command timing 0 ? 1 there are two separate command timing registers, each with identical fields. these registers are located at the following indexes: index command timing 3bh command timing 0 3eh command timing 1 the command timing register for each timing set controls how long a pc card cycle ? s command (that is, -oe, -we, -iord, -iowr; see table 2 on page 20 ) active time will be, in terms of the number of internal clock cycles. the overall command timing length c is programmed by selecting a 2-bit prescaling value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command timing length according to the following formula: c = ( n pres n val ) + 1 the value of c , representing the number of internal clock cycles for a command, is then multiplied by the internal clock ? s period to determine the command active time (see ? pc card bus timing calculations ? on page 109 for further discussion). 00 n pres = 1 01 n pres = 16 10 n pres = 256 11 n pres = 8192 register name: command timing 0 ? 1 index: 3bh, 3eh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 command prescalar select command multiplier value rw:00 rw:000110/001111 1 1. timing set 0 (index 3bh) resets to 06h for socket timing equal to standard at-bus-based cycle times. timing set 1 (3eh) resets to 0fh for socket timings equal to standard at-bus timing using one additional wait state.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 86 datasheet bits 5:0 ? command multiplier value this field indicates an integer value n val from 0 to 63; it is combined with a prescalar value (bits 7:6) to control the length that a command is active. bits 7:6 ? command prescalar select this field chooses one of four prescalar values n pres that are combined with the value of the command multiplier value (bits 5:0) to control the length that a command is active. 11.3 recovery timing 0 ? 1 there are two separate recover timing registers, each with identical fields. these registers are located at the following indexes: index recovery timing 3ch recovery timing 0 3fh recovery timing 1 the recovery timing register for each timing set controls how long a pc card cycle ? s command (that is, -oe, -we, -iord, -iowr; see table 2 on page 20 ) recovery will be, in terms of the number of internal clock cycles. the overall command recovery timing length r is programmed by selecting a 2-bit prescaling value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command recovery timing length according to the following formula: r = ( n pres n val ) + 1 the value of r , representing the number of internal clock cycles for command recovery, is then multiplied by the internal clock ? s period to determine the command recovery time (see ? pc card bus timing calculations ? on page 109 for further discussion). 00 n pres = 1 01 n pres = 16 10 n pres = 256 11 n pres = 8192 register name: recovery timing 0 ? 1 index: 3ch, 3fh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 recovery prescalar select recovery multiplier value rw:00 rw:000011
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 87 bits 5:0 ? recovery multiplier value this field indicates an integer value n val from 0 to 63; it is combined with a prescalar value (bits 7:6) to control the length of recovery time after a command is active. bits 7:6 ? recovery prescalar select this field chooses one of four prescalar values n pres that are combined with the value of the recovery multiplier value (bits 5:0) to control the length of recovery time after a command is active. 00 n pres = 1 01 n pres = 16 10 n pres = 256 11 n pres = 8192
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 88 datasheet 12.0 ata mode operation the pd67xx pc card interfaces can be dynamically configured to support a pc card ? compatible ata disk interface (commonly known as ? ide ? ) instead of the standard pc card interface. disk drives that can be made mechanically-compatible with pc card dimensions can thus operate through the socket using the ata electrical interface. configuring a socket to support ata operation changes the function of certain card socket signals to support the needs of the ata disk interface. table 17 lists each interface pin and its function when a pd67xx card socket is operating in ata mode. refer to application note an-pd5, configuring pcmcia sockets for ata drive interface , for more information. all register functions of the pd67xx are available in ata mode, including socket power control, interface signal disabling, and card window control. no memory operations are allowed in ata mode. table 17. ata pin cross-reference (sheet 1 of 3) pc card socket pin number function pc card interface ata interface 1 ground ground 2d3 d3 3d4 d4 4d5 d5 5d6 d6 6d7 d7 7-ce1-cs0 8 a10 n/c 9 -oe -ata (always low) 10 a11 n/c 11 a9 cs1* 12 a8 n/c 13 a13 n/c 14 a14 n/c 15 -we n/c 16 -ireq ireq 17 vcc vcc 18 vpp1 n/c 19 a16 n/c 20 a15 n/c 21 a12 n/c 22 a7 n/c 1. not supported by the pd67xx.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 89 23 a6 n/c 24 a5 n/c 25 a4 n/c 26 a3 n/c 27 a2 a2 28 a1 a1 29 a0 a0 30 d0 d0 31 d1 d1 32 d2 d2 33 -iois16 -iois16 34 ground ground 35 ground ground 36 -cd1 -cd1 37 d11 d11 38 d12 d12 39 d13 d13 40 d14 d14 41 d15 d15 42 -ce2 -cs1 43 vs1 vs1 44 -iord -iord 45 -iowr -iowr 46 a17 n/c 47 a18 n/c 48 a19 n/c 49 a20 n/c 50 a21 n/c 51 vcc vcc 52 vpp2 n/c 53 a22 n/c 54 a23 vu 55 a24 -m/s 56 a25 csel 57 vs2 vs2 table 17. ata pin cross-reference (sheet 2 of 3) pc card socket pin number function pc card interface ata interface 1. not supported by the pd67xx.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 90 datasheet 58 reset reset* 59 -wait iochrdy 60 -inpack dreq1 61 -reg -dack 1 62 -spkr -led 63 -stschg -pdiag 1 64 d8 d8 65 d9 d9 66 d10 d10 67 -cd2 -cd2 68 ground ground table 17. ata pin cross-reference (sheet 3 of 3) pc card socket pin number function pc card interface ata interface 1. not supported by the pd67xx.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 91 13.0 using gpstb pins for external port control (pd6722 only) the pd6722 provides pins that can be programmed to function as general-purpose strobes to external latches or buffers, allowing them to serve as read ports or write ports mapped into the pd6722 register set. configuring a gpstb pin as a read port allows an easy way to read additional card status such as vs1# and vs2# levels, a card socket microswitch status, a card port cover microswitch status, card eject solenoid position status, or general system signal status. configuring a gpstb pin as a write port allows an easy way to control additional features such as card-state leds, card mechanism solenoids, or motor eject mechanisms. 13.1 control of gpstb pins the extension control 2 register controls the gpstb pins. for the pd6722, the a_gpstb pin is controlled by the extension control 2 register at socket a (index 2fh, extended index 0bh), and the b_gpstb pin is controlled by the extension control 2 register at socket b (index 6fh, extended index 0bh). the following table summarizes how the gpstb pins are configured and how data is accessed from external ports created by using a gpstb pin to control an external read or write port. programming the extension control 2 register there is one extension control 2 register per gpstb pin. each register has identical gpstb control bits, as follows. see also the description of this register in ? extension control 2 (pd6722 only) ? on page 83 . table 18. registers for control and data of gpstb pins pin name gpstb control access external port data access a_gpstb (pd6722) set register 2e to 0bh, access extension control 2 register at 2f set register 2e to 0ah, access external data register at 2f b_gpstb (pd6722) set register 6e to 0bh, access extension control 2 register at 6f set register 6e to 0ah, access external data register at 6f register name: extension control 2 index: 2fh and 6fh extended index: 0bh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved active-high gpstb gpstb on iow* gpstb on ior* totem-pole gpstb reserved rw:00 rw:0 rw:0 rw:0 rw:0 rw:00
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 92 datasheet bit 5 allows programming of the active level of gpstb, with the default being active-low. setting bit 5 to ? 1 ? causes a gpstb output to be low normally and high (active) upon external data access. bit 4 controls use of the respective gpstb pin as a write strobe for an external general-purpose latch. when the respective extended index is set to 0ah and the index register is set to the respective 2fh or 6fh setting, i/o writes that access address 3e1h will result in the respective gpstb signal being driven active for the duration of the isa bus iow* signal being driven low. bit 3 controls use of the respective gpstb pin a read strobe for an external general-purpose buffer. when the respective extended index is set to 0ah and the index register is set to the respective 2fh or 6fh setting, i/o reads that access address 3e1h will result in the respective gpstb signal being driven active for the duration of the isa bus ior* signal being driven low. bit 2 cause the gpstb output to be totem-pole instead of the default open-collector configuration. when gpstb outputs are totem-pole, their ? high ? level is driven to the voltage of the ? +5v ? pin, instead of to high-impedance. if neither bit 3 nor bit 4 is set, the respective gpstb pin functions as a reserved input in a pd6722 that is an internal pull-up to the ? +5v ? pin. this internal pull-up is turned off whenever the gpstb pin is configured as a general-purpose strobe, or when the respective socket ? s pull-up control bit is set to ? 1 ? . bits 7:6 and 1:0 are reserved and must be programmed to ? 0 ? . these bits should not be used as scratchpad bits. external data port access through the external data register data to be accessed from an external read or write port is mapped to the respective external data register at extended index 0ah. this allows external data to be accessed as if it were a register in the pd67xx register set. to achieve this mapping, the external data port ? s buffer or latch data connections should be made to sd[15:8] of the system bus for 16-bit systems, and to sd[7:0] of the system bus for 8-bit systems. to support readback of data written to an external i/o port by use of a gpstb pin, a shadow of the external data register exists, which is read when an i/o read is done from the external data register location corresponding to a gpstb pin programmed as a write strobe. for more information on the socket a and socket b versions of this register, see the description of this register in ? external data (pd6722 only, socket a, index 2fh) ? on page 81 and ? external data (pd6722 only, socket a, index 6fh) ? on page 82 . register name: external data index: 2fh extended index: 0ah register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 external data 7 external data 6 external data 5 external data 4 external data 3 external data 2 external data 1 external data 0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 93 13.2 example implementations of gpstb-controlled read and write ports in this mode, extension control 2 register bit 4 is set to ? 1 ? enabling the gpstb pin to function as a write strobe. writes to the respective extended index 0ah cause the respective gpstb to go active (low) for the duration of the system ? s iow* pulse. on writes, data is written to both the external latch and the internal shadow copy of the external data register. a read of the respective extended index 0ah would produce the last value written to the latch. connection of the isa bus pwrgood signal to the external latch ensures that the latch assumes all ? 0 ? s at its outputs when the pd67xx is reset. figure 13. example gpstb write port (extension control 2 bits 4:3 are ? 10 ? ) iow* iow* sd[15:0] sd[15:0] gpstb latch ck o0 d res ext_wr* sd[15:8] (16-bit bus) general- purpose outputs o7 pwrgood pull-up ? ? pull-up resistor, or set extension control 2 bit 2 to ? 1 ? for totem-pole output. (for example, ? 374) pd6722 figure 14. example gpstb read port (extension control 2 bits 4:3 are ? 01 ? ) ior* ior* sd[15:0] sd[15:0] gpstb tristate buffer d7 o d0 oe ext_rd* sd[15:8] (16-bit bus) general- purpose inputs ? pull-up resistor, or set extension control 2 bit 2 to ? 1 ? for totem-pole output. pull-up ? (for example, ? 244) pd6722
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 94 datasheet in this mode, extension control 2 register bit 3 is set to ? 1 ? , enabling the respective gpstb pin to function as a read strobe. reads from the corresponding extended index 0ah cause gpstb to go active (default active level is low) for the duration of the system ? s ior* pulse. note: data is still written to the shadowed external data register on writes to extended index 0ah but is not visible. 13.3 gpstb in suspend mode gpstb read and write strobes operate while the device is in suspend mode, but they are not allowed when the device is in hardware-assisted ? super-suspend ? mode (aen held high while in suspend mode). a clock to the pd6722 is not required for the external signal at gpstb to occur, but shadowing of write values in the internal register at extended index 0ah requires that the pd67xx is not in suspend mode so there is an active internal clock for register writes.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 95 14.0 vs1# and vs2# voltage detection the pd6722 provides support for vs1# and vs2# voltage sense for environments where special low-voltage keyed pc card sockets are to be used. with a low-voltage keyed socket, it is necessary to determine the operating voltage range of a card before applying power to it. the pd6722 supports reading of the levels on a socket ? s vs1# and vs2# pins through a uniform extended register programming model using socket b extended register 0ah. the programming model is as follows: for voltage detection on the pd6710, refer to the 5v_det pin. on the pd6722, the b_gpstb pin is programmed as a general-purpose read strobe. the vs1# and vs2# pins from the a and b sockets are connected to the external half of a ? 244 buffer as follows (which allows socket a vs1 and vs2 to appear as bits 0 and 1, and socket b vs1 and vs2 to appear as bits 2 and 3): register name: external data index: 6fh extended index: 0ah register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 external data 7 external data 6 external data 5 external data 4 b_vs2 input b_vs1 input a_vs2 input a_vs1 input rw:0 rw:0 rw:0 rw:0 r:0 r:0 r:0 r:0
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 96 datasheet figure 15. vs1# and vs2# sensing on a pd6722 (socket b extension control 2 bit 3 is ? 1 ? ) pd6722 ior* ior* sd[15:0] sd[15:0] b_gpstb tristate buffer (such as 1/2 of a ? 244) d3 d0 oe vs_rd* sd[11:8] +5v 5-v supply socket a socket b pin 43 pin 57 pin 43 pin 57 vs1# vs2# vs1# vs2# (16-bit bus) ? pull-up resistor, or set extension control 2 bit 2 to ? 1 ? for totem-pole output. ?
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 97 15.0 dma operation (pd6722 only) 15.1 dma capabilities of the pd6722 the pd6722 include support of a dma-capable pc card slave and the movement of dma data to/ from the card with the isa bus as a dma master. only one socket at a time should be enabled for dma transfer because the isa bus dma handshake signals are shared between both socket interfaces. dma transfers to and from the dma-capable pc card may be 8- or 16-bit, as indicated by the size of the isa bus dma cycle. note: transfer size at socket interface is the same as transfer size on an isa bus. for 8-bit dma transfers, connect pd6722 dma handshake signals to isa bus dma channels 0, 1, 2, or 3. for 16- bit transfers, connect pd6722 dma handshake signals to isa bus dma channels 5, 6, or 7. 15.2 dma-type pc card cycles transfer of dma data to or from a card is achieved through use of a special dma-type pc card interface cycle. this cycle is defined to not conflict with standard pc card memory or i/o cycles. a card that is dma-capable can distinguish pc card interface cycle types presented by the pd6722 according to the following table: note: bits 7 and 6 of the extension control 1 register must be nonzero for table 19 to be true; otherwise only standard pc card cycles will be issued to the card. the pc card address is also undefined during the dma read or write cycle. card dma data read and write cycles transfer dma data to or from a dma-capable pc card. these cycles are distinguished from normal card i/o cycles by the -reg signal being high during the cycle, which is an undefined condition in the pc card standard. table 19. four card cycle types for dma-type pc card interface socket interface cycle type function of -we/-oe function of -iord/-iowr function of -reg card memory read/write data transfer signaling always inactive high always inactive high attribute memory read/write data transfer signaling always inactive high always low card i/o read/write always inactive high data transfer signaling low = non-dma i/o cycle card dma data read/write terminal count outputs data transfer signaling high = dma cycle
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 98 datasheet 15.3 isa bus dma handshake signal a dma request from the card is passed to the isa bus as long as the socket interface fifo is empty. irq10 is used as the dma request output to the isa bus when bit 2 of the misc control 2 register is ? 1 ? . when bit 2 of the misc control 2 register is ? 1 ? , irq9 is redefined as the active-low dma acknowledge input from the isa bus. this signal must remain active for all dma transfers through the pd6722. terminal counts are passed through to the card from the pd6722 -vpp_valid pin when bit 6 of the misc control 2 register is ? 1 ? . for a dma write process, the last-cycle terminal count condition is indicated by -oe being active-low during a card dma data read cycle. for a dma read process, terminal count is indicated by -we being active-low during the last card cycle. 15.4 configuring the pd6722 registers for a dma transfer program the registers as follows to configure a pd6722 socket interface for dma transfer to/from a dma-capable pc card: 1. select which pin on the pc card interface will serve as the dma request input. 2. configure the socket interface as i/o-capable. 3. prevent dual-interpretation of socket interface dma handshake signals. 4. set the dma enable bit. 15.4.1 programming the dma request pin from the card the pd6722 allows selection of one from three pc card interface inputs to be redefined as the dma request input, and it also allows programming of the active level of the selected input. this is done by setting bits 7 and 6 of the extension control 1 register to the desired values matching those of the dma-capable pc card to be used. once this selection of dma request input is complete, the pc card interface is configured at the signal level for dma card interfacing. the following table shows how the pd6722 socket interface signals are redefined when a card is in dma card interface mode: figure 16. dma handshake connections to the isa bus to make the pd6722 dma-capable pd6722 irq10 irq9 -vpp_valid isa bus dreq -dack tc
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 99 notice that the dma acknowledge to the card as -reg high is only active during the actual dma read or write card cycle. this means there is no mechanism to deassert dack to the card: the card must understand that receiving the first dma cycle is its dma acknowledgment. 15.4.2 configuring the socket interface for i/o for dma support, bit 5 of the interrupt and general control register must be set to ? 1 ? to put the card interface in i/o card interface mode. 15.4.3 preventing dual interpretation of dma handshake signals if the wp/-iois16 pin is being used as the dma request line, the following should be considered: 1. bit 4 of the interface status register is now the level of the dma request line from the card. 2. bit 5 of the socket ? s two i/o window control registers should be set to ? 0 ? . if a socket ? s bvd2/-spkr pin is being used as the dma request line, speaker or led output from that socket is not available. if -inpack is selected as the dma request input, then bit 7 of the misc control 1 register should be set to ? 0 ? to disable use of this signal as input acknowledge control. standard i/o card interface signal name dma-capable card interface signal usage when signal redefinition for dma interface is effective -iois16 -iois16 or may be selected as the active-low dma request input extension control 1 register bits 7-6 = ? 10 ? (bvd2/) -spkr/-led -spkr/-led or may be selected as the active- low dma request input extension control 1 register bits 7-6 = ? 11 ? -inpack -inpack or may be selected as the active-low dma request input extension control 1 register bits 7-6 = ? 01 ? -reg -reg during standard cycles, active-high dack during dma read/write cycles only during actual card dma read or write cycle -oe -oe during standard cycles, active-low -tc during dma write cycles during dma write cycles (that is, when -reg is high and -iord is low) -we -we during standard cycles, active-low -tc during dma read cycles during dma read cycles (that is, when -reg is high and -iowr is low) figure 17. card dma request and acknowledge handshake with terminal count -dreq dack a pc card pd6722 -reg -iois16, -spkr, or -inpack -iois16, -spkr, or -inpack -reg a a dma cycle is the dma acknowledge to the card. -tc -oe/-we -oe/-we
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 100 datasheet no other register bits require special settings to accommodate dma support on a socket interface. 15.4.4 turning on dma system the dma system bit (bit 6 of the misc control 2 register) should be programmed to ? 1 ? to allow dma operation and to redefine isa bus interface pins for dma support as in figure 16 . 15.4.5 the dma transfer process as soon as the selected dma request input from the card becomes active (low) and the fifo empties, irq10 becomes active (high), signifying a dma request to the system. the system then responds with an active (low) -dack at irq9, which enables the pd6722 to decode any isa bus dma transfers that may occur and perform the corresponding transfers at the card. normal card i/ o or memory reads or writes may be interspersed with dma read and write cycles. 15.4.6 terminal count to card at conclusion of transfer at the conclusion of each transfer process, systems send active (high) tc (terminal count) pulses to the -vpp_valid pin during the last dma cycles to the pd6722. for a dma write cycle, tc active is signaled at the socket interface as the -oe pin going low during dma-type read cycles from the pc card. for a dma read cycle, tc active is signaled as the -we pin going low during dma-type write cycles to the pc card.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 101 16.0 electrical specifications 16.1 absolute maximum ratings caution: stresses above those listed may cause permanent damage to system components. these are stress ratings only; functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect system reliability. 16.2 dc specifications ambient temperature under bias 0 c to 70 c storage temperature ? 65 c to 150 c voltage on any pin (with respect to ground) ? 0.5 volts to 0.5 volts greater than voltage of +5v pin, respective to ground operating power dissipation 500 mw suspend power dissipation 10 mw power supply voltage 7 volts injection current (latch up) 25 ma table 20. general dc specifications symbol parameter min max unit conditions c in input capacitance 10.0 pf c out output capacitance 10.0 pf i il input leakage ? 10.0 10.0 a0 < v in < respective v cc supply pin i pu internal pull-up current ? 30 ? 400 a table 21. pc card bus interface dc specifications (sheet 1 of 2) symbol parameter min max unit conditions socket_vcc 5v power supply voltage 4.5 5.5 v normal operation socket_vcc 3v power supply voltage 3.0 3.6 v v ih input high voltage 2.0 v core_vdd = 3.0 v, misc control 2 register, bit 3 is ? 0 ? 2.0 v core_vdd = 4.5 v, misc control 2 register, bit 3 is ? 1 ? v il input low voltage 0.8 v core_vdd = 3.6 v, misc control 2 register, bit 3 is ? 0 ? 0.8 v core_vdd = 5.5 v, misc control 2 register, bit 3 is ? 1 ?
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 102 datasheet v ihc input high voltage cmos 0.7 v dd v core_vdd = 4.5 v, misc control 2 register, bit 3 is ? 0 ? v ilc input low voltage cmos 0.2 v dd v core_vdd = 5.5 v, misc control 2 register, bit 3 is ? 0 ? v oh output high voltage 2.4 v at rated i oh , respective socket_vcc = 3.0 v v ohc output high voltage cmos socket_vc c ? 0.5 v at rated i ohc , respective socket_vcc = 3.0 v v ol output low voltage 0.5 v at rated i ol i oh output high current ? 2ma respective socket_vcc = 3.0 v, v oh = 2.4v i ohc output high current cmos ? 1ma respective socket_vcc = 3.0 v, v ohc = socket_vcc ? 0.5 v i ol output low current 2 ma respective socket_vcc = 3.0 v, v ol = 0.5 v table 22. isa bus interface dc specifications (sheet 1 of 2) symbol parameter min max unit conditions isa_vcc 5v power supply voltage 4.5 5.5 v normal operation isa_vcc 3v power supply voltage 3.0 3.6 v normal operation v ih 1 input high voltage 2.0 v core_vdd = 3.0 v v il 1 input low voltage 0.8 v core_vdd = 3.6 v v ihc 1 input high voltage cmos 0.7 v dd 1 v core_vdd = 4.5 v v ilc 1 input low voltage cmos 0.2 v dd 2 v core_vdd = 5.5 v v oh output high voltage 2.4 v at rated i oh , isa_vcc = 3.0 v v ohc output high voltage cmos isa_vcc ? 0.5 v at rated i ohc , isa_vcc = 3.0 v v ol output low voltage 0.5 v at rated i ol i oh output current high, 2-ma-type driver ? 2ma isa_vcc = 3.0 v, v oh = 2.4 v output current high, 12-ma-type driver ? 5ma output current high, 16-ma-type driver ? 5ma i ohc output current high cmos, 2-ma-type driver ? 1ma isa_vcc = 3.0 v, v ohc = isa_vcc ? 0.5 v output current high cmos, 12-ma-type driver ? 1ma output current high cmos, 16-ma-type driver ? 1ma 1. when the core_vdd voltage is 3.3 v, input thresholds are ttl compatible; when the core_vdd voltage is 5 v, input thresholds are cmos compatible. 2. the value of the input threshold level is dependent on the voltage applied to v dd pins of the pd67xx. table 21. pc card bus interface dc specifications (sheet 2 of 2) symbol parameter min max unit conditions
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 103 i ol output current low, 2-ma-type driver 2ma isa_vcc = 3.0 v, v ol = 0.5 v output current low, 12-ma-type driver 12 ma output current low, 16-ma-type driver 16 ma table 23. power control interface (+5v powered) dc specifications symbol parameter min max unit conditions +5v +5v supply voltage highest v cc ? 0.3 5.5 v v ih input high voltage 2.0 v +5v pin voltage = 4.5 v v il input low voltage 0.8 v +5v pin voltage = 5.5 v v oh output high voltage 2.4 v +5v pin voltage = 4.5 v, i oh = ? 5 ma v ohc output high voltage cmos +5v voltage ? 0.5 v +5v pin voltage = 4.5 v, i oh = ? 1 ma v ol output low voltage 0.5 v i oh output current high, 16-ma-type driver -5 ma respective +5v pin voltage = 4.5 v, v oh = 2.4 v i ohc output current high cmos, 16-ma-type driver ? 1ma respective +5v pin voltage = 4.5 v, v ohc = +5v pin voltage ? 0.5 v i ol output current low, 16-ma-type driver 16 ma respective +5v pin voltage = 4.5 v, v ol = 0.5 v table 24. operating current specifications symbol parameter min typ max unit conditions icc tot(1) power supply current, operating < 6 8 < 20 ma core_vdd = 3.3 v; +5v, socket_vcc, and isa_vcc = 5.0 v; p diss = < 85 mw icc tot(2) power supply current, suspend 1 < 150 a core_vdd = 3.3 v; +5v, socket_vcc, and isa_vcc = 5.0 v; p diss = < 2 mw icc tot(3) power supply current, super suspend, no clocks 1 < 20 a core_vdd = 3.3 v; +5v, socket_vcc, and isa_vcc = 5.0 v; p diss = < 1 mw 1. no cards in sockets; for pd6722, bit 5 of the dma control register is ? 1 ? . table 22. isa bus interface dc specifications (sheet 2 of 2) symbol parameter min max unit conditions 1. when the core_vdd voltage is 3.3 v, input thresholds are ttl compatible; when the core_vdd voltage is 5 v, input thresholds are cmos compatible. 2. the value of the input threshold level is dependent on the voltage applied to v dd pins of the pd67xx.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 104 datasheet 16.3 ac timing specifications this section includes system timing requirements for the pd67xx. timings are provided in nanoseconds (ns), at ttl input levels, with the ambient temperature varying from 0 c to 70 c, and v cc varying from 3.0 to 3.6 v or 4.5 to 5.5 v dc. the at bus speed is 10 mhz unless otherwise noted. note that an asterisk (*) denotes an active-low signal for the isa bus interface, and a dash (-) denotes an active-low signal for the pc card socket interface. additionally, the following statements are true for all timing information: all timings assume a load of 50 pf. ttl signals are measured at ttl threshold; cmos signals are measured at cmos threshold. 16.4 isa bus timing table 25. list of ac timing specifications title page number table 26 ? isa bus timing ? 104 table 27 ? reset timing ? 107 table 28 ? pulse mode interrupt timing ? 107 table 29 ? general-purpose strobe timing ? 108 table 30 ? input clock specification ? 108 table 31 ? memory read/write timing (word access) ? 111 table 32 ? word i/o read/write timing ? 112 table 33 ? pc card read/write timing when system is 8-bit ? 113 table 34 ? normal byte read/write timing ? 114 table 35 ? 16-bit system to 8-bit i/o card: odd byte timing ? 115 table 36 ? dma read cycle timing (pd6722 only) ? 116 table 37 ? dma write cycle timing (pd6722 only) ? 118 table 38 ? dma request timing (pd6722 only) ? 119 table 26. isa bus timing (sheet 1 of 2) symbol parameter min max unit t 1 memcs16* active delay from la[23:17] valid 40 ns t 1a la[23:17] setup to ale inactive 30 ns t 1b la[23:17] hold from ale inactive 5 ns t 2 iocs16* active delay from sa[15:0] 1 40 ns 1. aen must be inactive for t 2 , t 3 , and t 6 timing specifications to be applicable. 2. command is defined as ior*, iow*, memr*, or memw*. 3. except for valid card memory writes, which are zero wait state when internal write fifo is not full. 4. if card is removed during a card access cycle, iochrdy is three-stated without waiting for end of command. 5. based on 25-mhz internal clock, produced either by an internal synthesizer and 14.318-mhz signal applied to clk pin, or by supplying 25 mhz directly to clk pin and bypassing the internal synthesizer.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 105 t 2a iocs16* inactive delay from sa[15:0] 1 40 ns t 3 sa[16:0], sbhe* setup to any command active 1, 2 la[23:17] latching by ale to any command active 30 90 ns ns t 4 any command active to iochrdy inactive (low) 3 40 ns t 4a iochrdy three-state from command inactive 4 530 t 5 memcs16* inactive delay from unlatched la[23:17] 40 ns t 6a iow* or ior* pulse width 1 140 ns t 6b memw* or memr* pulse width 1 180 ns t 7 any command inactive to next command active 100 ns t 8 address or sbhe* hold from any command inactive 0 ns t 9 data valid from memw* active 5 data valid from iow* active 40 40 ns ns t 10 data hold from memw* inactive data hold from iow* inactive 5 5 ns ns t 11 data delay from ior* active, for internal registers 0 130 ns t 12 data delay from iochrdy active 15 ns t 13 data hold from ior* or memr* inactive 0 30 ns t 14 aen inactive setup to valid ior* or iow* active 40 ns t 15 aen hold from ior* or iow* inactive 5 ns t 16 refresh* inactive setup to valid memr* or memw* active 40 ns t 17 refresh* inactive hold from memr* or memw* active 0 ns t 18 memcs16* active delay from sa[16:12] valid 40 ns t 19 *zws delay from memw* active 30 ns t 20 *zws hold from memw* inactive 15 ns table 26. isa bus timing (sheet 2 of 2) symbol parameter min max unit 1. aen must be inactive for t 2 , t 3 , and t 6 timing specifications to be applicable. 2. command is defined as ior*, iow*, memr*, or memw*. 3. except for valid card memory writes, which are zero wait state when internal write fifo is not full. 4. if card is removed during a card access cycle, iochrdy is three-stated without waiting for end of command. 5. based on 25-mhz internal clock, produced either by an internal synthesizer and 14.318-mhz signal applied to clk pin, or by supplying 25 mhz directly to clk pin and bypassing the internal synthesizer.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 106 datasheet figure 18. bus timing ? isa bus la[23:17] sa[16:0] sbhe* memcs16* iocs16* memr*, memw* ior*, iow* iochrdy write data read data valid valid valid t 1 t 2 t 3 t 4 t 5 t 6a , t 6b t 7 t 8 t 9 t 10 t 12 t 13 aen t 14 t 15 refresh* t 16 t 17 t 18 ale t 2a t 1a t 1b t 4a t 20 t 19 zws* t 11
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 107 16.4.1 reset timing 16.4.2 system interrupt timing table 27. reset timing symbol parameter min max units t 1 pwrgood generated reset pulse width 500 ns t 2 clock active before end of reset 1 500 ns t 3 end of pwrgood generated reset to first command 500 ns 1. clock input must be active for a minimum of 500 ns before pwrgood goes active to allow sufficient internal clocks to initialize internal circuitry. figure 19. reset timing table 28. pulse mode interrupt timing symbol parameter min max t 1 irq[xx] low or high 2 clk ? 10 ns 2 clk + 10 ns t 1 memr*, memw* t 3 pwrgood ior*, iow* clk t 2
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 108 datasheet 16.4.3 general-purpose strobe timing (pd6722 only) 16.4.4 input clock specification figure 20. pulse mode interrupt timing table 29. general-purpose strobe timing symbol parameter min max units t 1 gpstb delay after ior* or iow* active 40 ns t 2 gpstb delay after ior* or iow* inactive 40 ns figure 21. general-purpose strobe timing table 30. input clock specification (sheet 1 of 2) symbol parameter min max units conditions t 1 clk pin input rise time 1 7 ns t 2 clk pin input fall time 1 7 ns t 3 clk input low period 0.4 t clkp 0.6 t clkp ns t 4 clk input high period 0.4 t clkp 0.6 t clkp ns v center center voltage at which period specified 0.5 v dd 0.5 v dd v irq[xx] high-z high-z t 1 t 1 high-z = high impedance note: each time indicated is 2 clock periods of the clk input to the pd67xx, independent of setting of the bypass frequency synthesizer bit. ior*, iow* t 1 gpstb t 2
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 109 16.4.5 pc card bus timing calculations calculations for minimum pc card cycle setup, command, and recovery timings are made by first calculating factors derived from the applicable timer set ? s timing registers and then by applying the factor to an equation relating it to the internal clock period. the pc card cycle timing factors, in terms of the number of internal clocks, are calculated as follows: s = ( n pres n val ) + 1 c = ( n pres n val ) + 1 r = ( n pres n val ) + 1 t clkp input clock period, internal clock 69.84 ? 0.1% 69.84 + 0.1% ns normal synthesizer operation. misc control 2 register, bit 0 = ? 0 ? . clk pin at 14.318 mhz. t clkp input clock period, external clock 40 ? 0.1% 40 + 0.1% ns synthesizer bypassed. misc control 2 register, bit 0 = ? 1 ? . clk pin at 25 mhz. v ihmin clk input high voltage 2.0 v core_vdd = 3.0 v v ilmax clk input low voltage 0.8 v core_vdd = 3.6 v v ihcmin clk input high voltage 0.7 v dd v core_vdd = 4.5 v v ilcmax clk input low voltage 0.2 v dd v core_vdd = 5.5 v figure 22. input clock specification table 30. input clock specification (sheet 2 of 2) symbol parameter min max units conditions t 1 v ilmax , v ilcmax t 2 t 3 t 4 t clkp clk v ihmin , v ihcmin v center
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 110 datasheet n pres and n val are the specific selected prescaler and multiplier value from the timer set ? s setup, command, and recovery timing registers (see ? timing registers ? on page 84 for a description of these registers). from this, a pc card cycle ? s setup, command, and recovery time for the selected timer set are calculated as follows: setup time = ( s tcp ) 10 ns command time = ( c tcp ) 10 ns recovery time = ( r tcp ) 10 ns when the internal synthesizer is used, the calculation of the internal clock period tcp is: tcp = t clkp 4/7 where t clkp is the period of the clock supplied to the clk input pin. an input frequency of 14.318 mhz at the clk input pin results in an internal clock period of tcp = 40 ns. when the internal synthesizer is bypassed, tcp = t clkp . an input frequency of 25 mhz in this circumstance would also result in an internal clock period of tcp = 40 ns. the timing diagrams that follow were derived for a pd67xx using the internal synthesizer and a 14.318-mhz clk pin input. the internal clock frequency of the pd67xx is 7/4 of this incoming signal ( tcp = 40 ns). the examples are for the default values of the timing registers for timer set 0, as follows: thus the minimum times for the default values are as follows: default minimum setup time = ( s tcp ) ? 10 ns = {2 40 ns} ? 10 ns = 70 ns default minimum command time = ( c tcp ) ? 10 ns = {7 40 ns} ? 10 ns = 270 ns default minimum recovery time = ( r tcp ) ? 10 ns = {4 40 ns} ? 10 ns = 150 ns timing register name (timer set 0) index value (default) resultant n pres resultant n val setup timing 0 3ah 01h 1 1 command timing 0 3bh 06h 1 6 recovery timing 0 3ch 03h 1 3
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 111 16.4.5.1 pc card socket timing table 31. memory read/write timing (word access) symbol parameter min max units t 1 -ce[2:1], -reg, address, and write data setup to command active 1 (s tc p ) ? 10 ns t 2 command pulse width 2 (c tc p ) ? 10 ns t 3 address hold and write data valid from command inactive 3 (r tc p ) ? 10 ns t 4 -wait active from command active 4 (c ? 2)tcp ? 10 ns t 5 command hold from -wait inactive (2 tcp) + 10 ns t 6 data valid from -wait inactive tcp + 10 ns t 7 data setup before -oe inactive (2 tcp) + 10 ns t 8 data hold after -oe inactive 0 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. for typical active timing programmed at 280 ns, maximum -wait timing is 190 ns after command active. figure 23. memory read/write timing -reg, -ce[2:1], t 1 t 2 t 4 t 3 -wait t 7 d[15:0] d[15:0] t 8 t 5 a[25:0] -oe, -we t 6 write cycle read cycle
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 112 datasheet table 32. word i/o read/write timing symbol parameter min max units t 1 -reg or address setup to command active 1 (s tcp ) ? 10 ns t 2 command pulse width 2 (c tc p ) ? 10 ns t 3 address hold and write data valid from command inactive 3 (r tc p ) ? 10 ns t 4 -wait active from command active 4 (c ? 2)tcp ? 10 ns t 5 command hold from -wait inactive (2 tcp) + 10 ns t ref card -iois16 delay from valid address (pc card specification) 35 ns t 6 -iois16 setup time before command end (3 tcp) + 10 ns t 7 -ce2 delay from -iois16 active 5 tc p ? 10 ns t 6 data valid from -wait inactive tcp + 10 ns t 9 data setup before -iord inactive (2 tcp) + 10 ns t 10 data hold after -iord inactive 0 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. for typical active timing programmed at 280 ns, maximum -wait timing is 190 ns after command active. 5. -iois16 must go low within 3tcp + 10 ns of the cycle beginning or -iois16 will be ignored and -ce will not be activated.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 113 figure 24. word i/o read/write timing table 33. pc card read/write timing when system is 8-bit symbol parameter min max units t 1 -reg or address setup to command active 1 (s tc p ) ? 10 ns t 2 command pulse width 2 (c tc p ) ? 10 ns t 3 address hold from command inactive 3 (r tc p ) ? 10 ns t 4 data setup before command inactive (2 tcp) + 10 ns t 5 data hold after command inactive 0 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . -iowr, -iord t 1 t 2 t 6 t 3 -iois16 t 7 -ce1 -reg, a[25:0] -ce2 d[15:0] t ref write cycle t 4 -wait t 5 t 9 d[15:0] t 10 t 8 read cycle
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 114 datasheet figure 25. pc card read/write timing when system is 8-bit (sbhe tied high) table 34. normal byte read/write timing symbol parameter min max units t 1 address setup to command active 1 (s tcp ) ? 10 ns t 2 command pulse width 2 (c tc p ) ? 10 ns t 3 address hold from command inactive 3 (r tc p ) ? 10 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . -iowr, -iord, t 1 t 2 t 3 -ce1 -reg, a[25:0] d[7:0] odd/even data d[15:8] xx -oe, -we d[7:0] read cycle t 5 t 4 write cycle read or write cycle odd/even data
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 115 figure 26. normal byte read/write timing table 35. 16-bit system to 8-bit i/o card: odd byte timing symbol parameter min max units t 1 address change to -iois16 inactive 4 (3tcp) + 10 ns t 2 -iois16 inactive to -ce2 inactive 20 ns t 3 -iois16 inactive to -ce1 active 20 ns t 4 address setup to command active 1 (s tc p ) ? 10 ns t 5 command pulse width 2 (c tcp ) ? 10 ns t 6 address hold from command inactive 3 (r tcp ) ? 10 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. -iois16 level from card should be valid before -iowr/-iord goes active. for a typical setup time of 70 ns, a pc card meeting the pcmcia specification for -iois16 from a[25:0] change will meet this condition. -reg, iowr, -iord, t 1 t 2 t 3 -ce1 a[25:0] -ce2 d[7:0] odd/even data d[15:8] xx -oe, -we write cycle read or write cycle d[7:0] read cycle odd/even data note: figure 26 applies to all other byte accesses, including odd i/o cycles where -iois16 is low.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 116 datasheet figure 27. 16-bit system to 8-bit i/o card: odd byte timing table 36. dma read cycle timing (pd6722 only) (sheet 1 of 2) symbol parameter min max units t 1 drq (irq10) and dack* (irq9) active to dma cycle begin 40 ns t 2 -ce[2:1], -reg, -iord, -oe, and write data setup to -iowr active 1 (s tc p ) ? 10 ns t 3 command: -iowr pulse width 2 (c tc p ) ? 10 ns t 4 recovery: -iowr inactive to end of cycle 3 (r tc p ) ? 10 ns t 5 -wait active from -iowr active (c ? 2)tcp ? 10 ns t 6 -wait inactive to -iowr inactive 2 tcp ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. based on an internal clock period of 40 ns (25 mhz). -reg, -iois16 t 3 -ce1 a[25:0] -ce2 d[7:0] odd data t 2 write cycle d[7:0] read cycle odd data d[15:8] xx read or write cycle -iowr, -iord t 4 t 5 t 6 t 1
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 117 t 7 system tc (-vpp_valid high) to -iowr ? 40 ns t 8 -iowr to begin of card tc (-we) 4 25 50 ns t 9 end of card tc (-we) to -iowr inactive 4 25 50 ns figure 28. dma read cycle timing table 36. dma read cycle timing (pd6722 only) (sheet 2 of 2) symbol parameter min max units 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. based on an internal clock period of 40 ns (25 mhz). -ce[2:1] t 2 t 3 t 5 t 4 -wait dma data[15:0] -vpp_valid t 6 -iowr to card (tc from system) irq9 -iord, -oe -reg (dack*) (high) (dack* to card) t 1 t 7 -we (tc to card) t 8 t 9 irq10 (drq)
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 118 datasheet table 37. dma write cycle timing (pd6722 only) symbol parameter min max units t 1 drq (irq10) and dack* (irq9) active to dma cycle begin 40 ns t 2 -ce[2:1], -reg, -iowr, -we, and write data setup to -iord active 1 (s tc p ) ? 10 ns t 3 command: -iord pulse width 2 (c tc p ) ? 10 ns t 4 recovery: -iord inactive to end of cycle 3 (r tc p ) ? 10 ns t 5 -wait active from -iord active (c ? 2)tcp ? 10 ns t 6 -wait inactive to -iord inactive 2 tcp ns t 7 system tc (-vpp_valid high) to -iord ? 40 ns t 8 -iord to begin of card tc (-oe) 4 25 50 ns t 9 end of card tc (-oe) to -iord inactive 4 25 50 ns t 10 data valid from -wait inactive tcp + 10 ns t 11 data setup before -oe inactive (2 tcp) +10 ns t 12 data hold after -oe inactive 0 ns 1. the setup time is determined by the value programmed into the setup timing register, index 3ah/3dh. using the timer set 0 default value of 01h, the setup time would be 70 ns. s = (n pres n val + 1), see ? pc card bus timing calculations ? on page 109 . 2. the command time is determined by the value programmed into the command timing register, index 3bh/3eh. using the timer set 0 default value of 06h, the command time would be 270 ns. c = (n pres n val + 1), see page 109 . 3. the recovery time is determined by the value programmed into the recovery timing register, index 3ch/3fh. using the timer set 0 default value of 03h, the hold (recovery) time would be 150 ns. r = (n pres n val + 1), see page 109 . 4. based on an internal clock period of 40 ns (25 mhz).
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 119 figure 29. dma write cycle timing table 38. dma request timing (pd6722 only) symbol parameter min max units t 1 dma request from socket interface to system 1 40 ns 1. after fifo empty, dma requests held off from being presented to the system until all write data to a card has been emptied from the socket interface fifo. -ce[2:1] t 2 t 3 t 5 t 4 -wait dma data[15:0] -vpp_valid t 6 -iord to card (tc from system) irq9 -iowr, -we -reg (dack*) (high) (dack* to card) t 1 -oe (tc to card) t 11 dma data[15:0] t 12 t 10 from card t 7 t 8 t 9 irq10 (drq)
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 120 datasheet figure 30. dma request timing -inpack, wp/-iois16, t 1 or bvd2/-spkr 2 (-dreq from card) irq10 (drq to system) 2 dma control register bits 7 and 6 define which of these three signals serve as the active-low dma request from the card.
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 121 17.0 package specifications 17.1 144-pin lqfp package notes: 1. dimensions are in millimeters (inches), and controlling dimension is millimeter. 2. before beginning any new design with this device, please contact intel corp. for the latest package information. pin 1 indicator 17.50 (0.689) ref pin 1 21 . 60 (0 . 850) 22.40 (0.882) 0.10 (0.004) 0.30 (0.012) 19.90 (0.783) 20.10 (0.791) 17.50 (0.689) ref 0.50 (0.0197) bsc 1.25 (0.049) 1.50 (0.059) 0 min 7 max 0.10 (0.004) 0.20 (0.008) 1.40 (0.055) 1.65 (0.065) 0.45 (0.018) 0.75 (0.030) 21.60 (0.850) 22.40 (0.882) 19.90 (0.783) 20.10 (0.791) 1.00 (0.039) ref 0.05 (0.002) 0.15 (0.006) pin 144 144-pin lqfp DZPD6710VCB
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 122 datasheet 17.2 208-pin mqfp package notes: 1. dimensions are in millimeters (inches), and controlling dimension is inches. 2. drawing above does not reflect exact package pin count. 3. before beginning any new design with this device, please contact intel corp. for the latest package information. pin 1 indicator 25.50 (1.004) ref 30.35 (1.195) 30.85 (1.215) 0.13 (0.005) 0.28 (0.011) 27.90 (1.098) 28.10 (1.106) 25.50 (1.004) ref 0.50 (0.0197) bsc 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 3.17 (0.125) 3.67 (0.144) 0 min 7 max 0.09 (0.004) 0.23 (0.009) 4.07 (0.160) max 0.40 (0.016) 0.75 (0.030) 0.25 (0.010) min 1.30 (0.051) ref pin 1 pin 208 208-pin mqfp spd6722qcce
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 123 17.3 208-pin lqfp package notes: 1. dimensions are in millimeters (inches), and controlling dimension is inches. 2. drawing above does not reflect exact package pin count. 3. before beginning any new design with this device, please contact intel corp. for the latest package information. 208-pin lqfp dzpd6722vcce pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) bsc pin 1 pin 208 1.60 (0.063) 0.15 (0.006)
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 124 datasheet 18.0 order numbers example the example order numbers for pd67xx devices are as follows: DZPD6710VCB product line: part number package type: lqfp temperature range: revision c = commercial portable products low-profile quad flat pack spd6722qcce product line: part number package type: mqfp temperature range: revision c = commercial portable products metric quad flat pack dzpd6722vcce product line: part number package type: lqfp temperature range: revision c = commercial portable products low-profile quad flat pack
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 125 19.0 appendix a 19.1 register summary tables 19.1.1 operation registers 19.2 chip control registers register name: index index: n/a register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device index socket index register index rw:0 rw:0 rw:000000 register name: data index: n/a register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data register name: chip revision index: 00h register per: chip register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 interface id revision r:10 r:0 r:0 r:001 1 1. value for the current stepping only.
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 126 datasheet register name: interface status index: 01h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3 bit 2bit 1bit 0 -vpp_valid rdy wp -cd2 -cd1 bvd2 bvd1 v pp valid card power on ready/busy* write protect card detect battery voltage detect r 1 r:0 r 2 r 3 r 4 r 5 1. bit 7 is the inversion of the value of the -vpp_valid pin (see table 1 on page 16 ). 2. bit 5 is the value of the rdy/-ireq pin (see table 2 on page 20 ). 3. bit 4 is the value of the wp/-iois16 pin (see table 2 ). 4. bits 3:2 are the inversion of the values of the -cd1 and -cd2 pins (see table 2 ). 5. bits 1:0 are the values of the bvd1/-stschg and bvd2/-spkr pins (see table 2 ). register name: power control index: 02h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 card enable compatibility bit auto-power v cc power compatibility bits v pp 1 power rw:0 rw:0 rw:0 rw:0 rw:00 rw:00 register name: interrupt and general control index: 03h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 ring indicate enable card reset* card is i/o enable management interrupts card irq select rw:0 rw:0 rw:0 rw:0 rw:0000 register name: card status change index: 04h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 card detect change ready change battery warning change battery dead or status change r:0 r:0 r:0 r:0 r:0 r:0 r:0 r:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 127 19.3 i/o window mapping registers register name: management interrupt configuration index: 05h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 management irq select card detect enable ready enable battery warning enable battery dead or status change enable rw:0000 rw:0rw:0rw:0rw:0 register name: mapping enable index: 06h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o map 1 enable i/o map 0 enable memcs16 full decode memory map 4 enable memory map 3 enable memory map 2 enable memory map 1 enable memory map 0 enable rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 register name: i/o window control index: 07h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 timing register select 1 compatibility bit auto-size i/o window 1 i/o window 1 size timing register select 0 compatibility bit auto-size i/o window 0 i/o window 0 size rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 register name: system i/o map 0 ? 1 start address low index: 08h, 0ch register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start address 7:0 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 128 datasheet register name: system i/o map 0 ? 1 start address high index: 09h, 0dh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 start address 15:8 rw:00000000 register name: system i/o map 0 ? 1 end address low index: 0ah, 0eh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 end address 7:0 rw:00000000 register name: system i/o map 0 ? 1 end address high index: 0bh, 0fh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 end address 15:8 rw:00000000 register name: card i/o map 0 ? 1 offset address low index: 36h, 38h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 offset address 7:1 0 1 rw:0000000 rw:0 1. this bit must be programmed to ? 0 ? . register name: card i/o map 0 ? 1 offset address high index: 37h, 39h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 15:8 rw:00000000
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 129 19.4 memory window mapping registers register name: system memory map 0 ? 4 start address low index: 10h, 18h, 20h, 28h, 30h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 start address 19:12 rw:00000000 register name: system memory map 0 ? 4 start address high index: 11h, 19h, 21h, 29h, 31h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 window data size compatibility bit scratchpad bits start address 23:20 rw:0 rw:0 rw:00 rw:0000 register name: system memory map 0 ? 4 end address low index: 12h, 1ah, 22h, 2ah, 32h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 end address 19:12 rw:00000000 register name: system memory map 0 ? 4 end address high index: 13h, 1bh, 23h, 2bh, 33h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 card timer select scratchpad bits end address 23:20 rw:00 rw:00 rw:0000 register name: card memory map 0 ? 4 offset address low index: 14h, 1ch, 24h, 2ch, 34h register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 offset address 19:12 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 130 datasheet 19.5 extension registers register name: card memory map 0 ? 4 offset address high index: 15h, 1dh, 25h, 2dh, 35h register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write protect reg setting offset address 25:20 rw:0 rw:0 rw:000000 register name: misc control 1 index: 16h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 inpack enable scratchpad bits speaker enable pulse system irq pulse management interrupt v cc 3.3v 5 v detect (pd6710) reserved (pd6722) rw:0 rw:00 rw:0 rw:0 rw:0 rw:0 r:x w:0 register name: fifo control index: 17h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 empty write fifo scratchpad bits 1 rw rw:0000000 1. because a write will flush the fifo, these scratchpad bits should be used only when card activity is guaranteed not to occur. register name: misc control 2 index: 1eh register per: chip register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 irq15 is ri out dma system (pd6722) three-state bit 7 drive led enable 5v core suspend low-power dynamic mode bypass frequency synthesizer rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:1 rw:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 131 register name: chip information index: 1fh register per: chip register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc card controller identification dual/single socket* pd67xx revision level reserved r:11 r:n 1 r:nnnn 2 r:n 3 1. the value for pd6710 is ? 0 ? , and the value for pd6722 is ? 1 ? . 2. this read-only value depends on the revision level of the pd67xx chip. 3. the value for pd6722 is ? 1 ? . register name: ata control index: 26h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a25/csel a24/m/s* a23/vu a22 a21 scratchpad bit speaker is led input ata mode rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 register name: extended index (pd6722 only) index: 2eh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extended index rw:00000000 register name: extended data (pd6722 only) index: 2fh register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extended data register name: data mask 0 (pd6722 only) index: 2fh extended index: 01h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data mask select 0 rw:00000000
pd6710/ ? 22 ? isa-to-pc-card (pcmcia) controllers 132 datasheet register name: data mask 1 (pd6722 only) index: 2fh extended index: 02h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 data mask select 1 rw:00000000 register name: extension control 1 (pd6722 only) index: 2fh extended index: 03h register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 dma enable pull-up control reserved led activity enable auto power clear disable v cc power lock rw:00 rw:0 rw:00 rw:0 rw:0 rw:0 register name: maximum dma acknowledge delay (pd6722 only) index: 2fh extended index: 04h register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 maximum dma acknowledge delay rw:00000000 register name: external data (pd6722 only) index: 2fh extended index: 0ah register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 external data 7 external data 6 external data 5 external data 4 external data 3 external data 2 external data 1 external data 0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 rw:0 register name: external data (pd6722 only) index: 6fh extended index: 0ah register per: socket register compatibility type: ext. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 external data 7 external data 6 external data 5 external data 4 external data 3 or b_vs2 input external data 2 or b_vs1 input external data 1 or a_vs2 input external data 0 or a_vs1 input rw:0 rw:0 rw:0 rw:0 r:0 r:0 r:0 r:0
isa-to-pc-card (pcmcia) controllers ? pd6710/ ? 22 datasheet 133 19.6 timing registers register name: extension control 2 (pd6722 only) index: 2fh and 6fh extended index: 0bh register per: socket register compatibility type: ext. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 reserved active-high gpstb gpstb on iow* gpstb on ior* totem-pole gpstb reserved rw:00 rw:0 rw:0 rw:0 rw:0 rw:00 register name: setup timing 0 ? 1 index: 3ah, 3dh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 setup prescalar select setup multiplier value rw:00 rw:000001 register name: command timing 0 ? 1 index: 3bh, 3eh register per: socket register compatibility type: 365 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 command prescalar select command multiplier value rw:00 rw:000110/001111 1 1. timing set 0 (index 3bh) resets to 06h for socket timing equal to standard at-bus-based cycle times. timing set 1 (3eh) resets to 0fh for socket timings equal to standard at-bus timing using one additional wait state. register name: recovery timing 0 ? 1 index: 3ch, 3fh register per: socket register compatibility type: 365 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 recovery prescalar select recovery multiplier value rw:00 rw:000011

datasheet 135 index symbols +5v 25 numerics 5v core bit 73 a a[25:0] 20 a21 bit 76 a22 bit 76 a23/vu bit 76 a24/m/s* bit 76 a25/csel bit 76 active-high gpstb bit 83 aen 17 ale 17 ata control register 75 ata mode description 88 overview 36 pin cross reference 88 ata mode bit 75 auto power clear disable bit 78 auto-power bit 50 auto-size i/o window 0 bit 58 auto-size i/o window 1 bit 59 b battery dead or status change bit 53 battery dead or status change enable bit 54 battery voltage detect bits 47 battery warning change bit 53 battery warning enable bit 54 bus sizing 35 bvd1/-stschg/-ri 23 bvd2/-spkr/-led 23 bypass frequency synthesizer bit 73 c c_sel 19 card detect bits 47 card detect change bit 53 card detect enable bit 55 card enable bit 50 card i/o map 0 ? 1 address offset high regis- ters 62 card i/o map 0 ? 1 address offset low regis- ters 62 card is i/o bit 52 card memory map 0 ? 4 offset address high registers 68 card memory map 0 ? 4 offset address low registers 67 card power on bit 48 card reset* bit 52 card status change register 52 card timer select bits 67 -cd[2:1] 22 -ce[2:1] 22 chip information register 74 chip revision register 46 clk 19 command multiplier value bits 86 command prescalar select bits 86 command timing 0 ? 1 registers 85 conventions bit naming 40 numbers and units 11 pin naming 14 register headings 39 d d[15:0] 20 data mask 0 ? 1 register 78 data mask select 0 ? 1 bits 78 data register 44
136 datasheet device index bit 41 dma enable bits 79 dma mode description 97 overview 36 dma read cycle timing 116 dma request timing 119 dma system bit 74 dma write cycle timing 118 drive led enable bit 73 dual/single socket* bit 75 e empty write fifo bit 72 enable manage int bit 51 end address 19:12 bits 66 23:20 bits 67 7:0 bits 61 extended data register 77 extended index register 77 extended register index bits 77 extension control 2 register 83 external data bits 81, 82 external data register 81 f fifo control register 72 form factor 1, ?? ? 123 functional blocks 30 g general-purpose strobe control 91 example implementations 93 overview 32 suspend mode 94 general-purpose strobe timing 108 gnd 25 gpstb 24 gpstb on ior* bit 83 gpstb on iow* bit 83 h host access to registers 36 i i/o map 0 enable bit 57 i/o map 0 ? 1 start address high registers 60 i/o map 1 enable bit 57 i/o window 0 size bit 58 i/o window 1 size bit 59 i/o window control register 58 ide 88 index register 41 -inpack 21 inpack enable bit 71 input clock specification 108 interface id bits 46 interface status register 47 interrupt and general control register 51 interrupts 30 -intr 18 iochrdy 17 iocs16* 17 -iois16 21 ior* 16 -iord 21 iow* 16 -iowr 21 -ireq 21 irq[14, 11, 7, 5:3] 18 irq10 18 irq10 as drq, description 32 irq12 as led_out*, description 31 irq12/led_out* 18 irq15 as ri_out*, description 31 irq15 is ri out bit 74 irq15/ri_out* 18 irq9 18 irq9 as dack*, description 32 isa bus timing 104 isa_vcc 19
datasheet 137 l la[23:17] 16 -led 23 led activity enable bit 79 led_out* 18 low-power dynamic mode 32 low-power dynamic mode bit 73 m management interrupt configuration register 54 management irq select bits 55 mapping enable register 55 memcs16 full decode bit 56 memcs16* 17 memory map 0 enable bit 56 memr* 17 memw* 17 misc control 1 register 70 misc control 2 register 72 n normal byte read/write timing 114 o odd byte timing 115 -oe 20 ordering information 124 p package 144-pin vqfp 121 208-pin pqfp 122 208-pin vqfp 123 pc card basics 27 bus timing calculations 109 read/write timing 113 socket timing 111 timing 36 pcmcia 27 pd67xx revision level bits 75 pin descriptions 12 ? 25 pin diagram 144-pin vqfp 13 208-pin pqfp or vqfp 14 pin usage summary 25 power consumption 34 power control register 48 power management 32 power-on configuration 25 setup 38 pull-up control bit 79 pulse management interrupt bit 70 pulse mode interrupt timing 107 pulse system irq bit 71 pwrgood 17 r rdy/-ireq 21 ready change bit 53 ready enable bit 54 ready/busy* bit 48 recovery multiplier value bits 87 recovery prescalar select bits 87 recovery timing 0 ? 1 registers 86 refresh* 17 -reg 20 reg setting bit 68 register index bits 41 reset 22 reset timing 107 revision bits 46 -ri 23 ri_out* 18 ring indicate enable bit 52 s sa[16:0] 16 sbhe* 16 sd[15:0] 16
138 datasheet setup multiplier value bits 84 setup prescalar select bit 85 setup timing 0 ? 1 registers 84 slot_vcc. see socket_vcc socket accessing specific registers 42 register per 39 socket index bit 41 socket power features 34 socket_vcc 23 speaker enable bit 71 speaker is led input bit 76 -spkr 23 spkr_out*/c_sel 19 -stschg 23 super-suspend mode, description 33 suspend bit 73 suspend mode, description 32 system interrupt timing 107 t three-state bit 7 bit 74 timing dma read cycle 116 dma request 119 dma write cycle 118 general-purpose strobe 108 isa bus 104 normal byte read/write 114 odd byte 115 pc card bus 109 pc card read/write 113 pc card socket 111 pulse mode interrupt 107 reset 107 system interrupt 107 word i/o read/write 112 timing register select 0 bit 58 timing register select 1 bit 59 totem-pole gpstb bit 83 v v cc 3.3v bit 70 v cc power bit 50 v cc power lock bit 78 -vcc_3 24 -vcc_5 24 voltage sense 95 ? 96 overview 32 v pp valid bit 48 vpp_pgm 24 -vpp_valid 19 vpp_vcc 24 v pp 1 power bits 50 w -wait 21 -we 21 window data size bit 65 windowing 27 word i/o read/write timing 112 wp/-iois16 21 write fifo 35 write protect bit 48, 69 z zws* 18

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